Paper Abstract and Keywords |
Presentation |
2019-03-05 13:30
Gateway Placement Optimization under Allowable Delay Constraint in HANETs: Considering Link Disruption Taichi Miya (Tokyo Tech), Kohta Ohshima (TUMSAT), Yoshiaki Kitaguchi, Katsunori Yamaoka (Tokyo Tech) IN2018-139 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In recent years, applications such as Intelligent Transportation System, Cyber-physical System, Wireless Sensor Networks, are deployed especially in urban areas, where the broadband mobile communication system is well developed, so the variety of applications running on ad-hoc networks tends to increase in future. Therefore, the demand of the interconnection of HANETs (heterogeneous ad-hoc networks) becomes growing. Moreover, because the communication entity is changing from humans to things, the communication delay that the network infrastructure should guarantee has been becoming stricter. In this paper, assuming a situation in which HANETs are directly interconnected by some protocol translators (called gateways, or GWs), we propose an optimum GW placement algorithm to maximize the allowable delay satisfaction rate under the assumption that each flow in the networks has an individual constraint of allowable delay. We evaluate our proposed method using a computer simulation. We also consider the impact of link disruption prediction for the performance improvement. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
ad-hoc network / interoperability / processing delay / transmission delay / allowable delay / GW placement optimization / / |
Reference Info. |
IEICE Tech. Rep., vol. 118, no. 466, IN2018-139, pp. 331-336, March 2019. |
Paper # |
IN2018-139 |
Date of Issue |
2019-02-25 (IN) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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IN2018-139 |
Conference Information |
Committee |
IN NS |
Conference Date |
2019-03-04 - 2019-03-05 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa Convention Center |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
General |
Paper Information |
Registration To |
IN |
Conference Code |
2019-03-IN-NS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Gateway Placement Optimization under Allowable Delay Constraint in HANETs: Considering Link Disruption |
Sub Title (in English) |
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Keyword(1) |
ad-hoc network |
Keyword(2) |
interoperability |
Keyword(3) |
processing delay |
Keyword(4) |
transmission delay |
Keyword(5) |
allowable delay |
Keyword(6) |
GW placement optimization |
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1st Author's Name |
Taichi Miya |
1st Author's Affiliation |
Tokyo Institute of Technology (Tokyo Tech) |
2nd Author's Name |
Kohta Ohshima |
2nd Author's Affiliation |
Tokyo University of Marine Science and Technology (TUMSAT) |
3rd Author's Name |
Yoshiaki Kitaguchi |
3rd Author's Affiliation |
Tokyo Institute of Technology (Tokyo Tech) |
4th Author's Name |
Katsunori Yamaoka |
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Tokyo Institute of Technology (Tokyo Tech) |
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Speaker |
Author-1 |
Date Time |
2019-03-05 13:30:00 |
Presentation Time |
20 minutes |
Registration for |
IN |
Paper # |
IN2018-139 |
Volume (vol) |
vol.118 |
Number (no) |
no.466 |
Page |
pp.331-336 |
#Pages |
6 |
Date of Issue |
2019-02-25 (IN) |
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