Paper Abstract and Keywords |
Presentation |
2019-03-01 10:25
A Study on Placement Constraints for Asynchronous Circuits with Bundled-data Implementation aimed for FPGAs Tatsuki Otake, Hiroshi Saito (UoA) VLD2018-123 HWS2018-86 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this work, we study placement constraints for asynchronous circuits with bundled-data implemen-tation aimed for Field Programmable Gate Arrays (FPGAs) to reduce the number of delay adjustments and to improve circuit performance. Placement constraints studied in this work are the placement constraints which can be used in a design tool supported by an FPGA vendor. In the experiment, we applied the placement constraints to two circuits and evaluated the number of delay adjustments, circuit performance, area, power consumption, and energy consumption. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Asynchronous circuits / FPGA / Placement constraints / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 118, no. 457, VLD2018-123, pp. 181-186, Feb. 2019. |
Paper # |
VLD2018-123 |
Date of Issue |
2019-02-20 (VLD, HWS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2018-123 HWS2018-86 |
Conference Information |
Committee |
HWS VLD |
Conference Date |
2019-02-27 - 2019-03-02 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa Ken Seinen Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Technology for System-on-Silicon, Hardware Security, etc. |
Paper Information |
Registration To |
VLD |
Conference Code |
2019-02-HWS-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Study on Placement Constraints for Asynchronous Circuits with Bundled-data Implementation aimed for FPGAs |
Sub Title (in English) |
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Asynchronous circuits |
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FPGA |
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Placement constraints |
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1st Author's Name |
Tatsuki Otake |
1st Author's Affiliation |
University of Aizu (UoA) |
2nd Author's Name |
Hiroshi Saito |
2nd Author's Affiliation |
University of Aizu (UoA) |
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Speaker |
Author-1 |
Date Time |
2019-03-01 10:25:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2018-123, HWS2018-86 |
Volume (vol) |
vol.118 |
Number (no) |
no.457(VLD), no.458(HWS) |
Page |
pp.181-186 |
#Pages |
6 |
Date of Issue |
2019-02-20 (VLD, HWS) |
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