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| Paper Abstract and Keywords | ||
| Presentation | 2019-03-01 11:15 Synthesis of Distributed Control Circuits for Dynamic Scheduling across Multiple Dataflow Graphs Sayuri Ota, Nagisa Ishiura (Kwansei Gakuin Univ.)  VLD2018-125 HWS2018-88 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This article presents a method for synthesizing circuits with distributed control from CDFGs (control data flow graphs). The distributed control attempts to harness a datapath with multiple FSMs (finite state machines) to adjust execution timing of operations dynamically, by which wasteful waits caused by variable latency units are reduced. Although Shimizu and Nakano proposed a distributed control scheme which allowed dynamic scheduling across multiple DFGs, they just presented example controllers which were manually designed. This article shows a formulation to make the multiple FSMs work in ensemble based on Nakano’s scheme, along with some restrictions on CDFGs to allow automatic synthesis. Experimental results shows that the synthesized circuits are on average about 13% larger than those based on conventional centralized controllers, but the critical path delay stays the same. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | high-level synthesis / variable latency units / control synthesis / distributed controller / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 118, no. 457, VLD2018-125, pp. 193-198, Feb. 2019. | |
| Paper # | VLD2018-125 | |
| Date of Issue | 2019-02-20 (VLD, HWS) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2018-125 HWS2018-88 |
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| Conference Information | |
| Committee | HWS VLD |
| Conference Date | 2019-02-27 - 2019-03-02 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2019-02-HWS-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Synthesis of Distributed Control Circuits for Dynamic Scheduling across Multiple Dataflow Graphs |
| Sub Title (in English) | |
| Keyword(1) | high-level synthesis |
| Keyword(2) | variable latency units |
| Keyword(3) | control synthesis |
| Keyword(4) | distributed controller |
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| 1st Author's Name | Sayuri Ota |
| 1st Author's Affiliation | Kwansei Gakuin University (Kwansei Gakuin Univ.) |
| 2nd Author's Name | Nagisa Ishiura |
| 2nd Author's Affiliation | Kwansei Gakuin University (Kwansei Gakuin Univ.) |
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| Speaker | Author-1 |
| Date Time | 2019-03-01 11:15:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2018-125, HWS2018-88 |
| Volume (vol) | vol.118 |
| Number (no) | no.457(VLD), no.458(HWS) |
| Page | pp.193-198 |
| #Pages | 6 |
| Date of Issue | 2019-02-20 (VLD, HWS) |
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