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Paper Abstract and Keywords
Presentation 2019-02-27 10:55
Efficient Challenge-Response Pairs Generation and Evaluation for PUF Circuit Using BIST Circuit During Manufacturing Test
Tomoki Mino, Shintani Michihiro, Michiko Inoue (NAIST) DC2018-75
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, counterfeited ICs have become a big problem for semiconductor supply chains. One of the countermeasures for the counterfeited chips is device identi cation using challenge response pairs (CRP) obtained from pysically unclonable function (PUF) circuit. However, previous PUF circuits require additional measurement and design cost to establish large number of the CRPs, and thus the cost is newly introduced into manufacturing cost. In this paper, we propose a novel method to generate the CRP during production test by conventionally used build-in self test (BIST) circuit. Because the production test and CRP generation are simultaneously conducted, the proposed method requires no additional cost and extra measurement. In addition, although it has been reported that the previous PUF circuits has a vulnerability against machine learning attacks, the proposed method is resis- tant to it because of device identi cation via the BIST circuit. Through proof-of-concept implementation on eld programmable gate array (FPGA), we demonstrate that the performance of a PUF circuit can be evaluated by the test pattern generated from the BIST circuit.
Keyword (in Japanese) (See Japanese page) 
(in English) Physically unclnable function circuit / Built-in self test / Challenge-response pair / Counterfeited chip / / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 456, DC2018-75, pp. 25-30, Feb. 2019.
Paper # DC2018-75 
Date of Issue 2019-02-20 (DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2019-02-27 - 2019-02-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Design and Test, etc. 
Paper Information
Registration To DC 
Conference Code 2019-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Efficient Challenge-Response Pairs Generation and Evaluation for PUF Circuit Using BIST Circuit During Manufacturing Test 
Sub Title (in English)  
Keyword(1) Physically unclnable function circuit  
Keyword(2) Built-in self test  
Keyword(3) Challenge-response pair  
Keyword(4) Counterfeited chip  
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1st Author's Name Tomoki Mino  
1st Author's Affiliation Nara Institute of Science and Technology (NAIST)
2nd Author's Name Shintani Michihiro  
2nd Author's Affiliation Nara Institute of Science and Technology (NAIST)
3rd Author's Name Michiko Inoue  
3rd Author's Affiliation Nara Institute of Science and Technology (NAIST)
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Speaker
Date Time 2019-02-27 10:55:00 
Presentation Time 25 
Registration for DC 
Paper # IEICE-DC2018-75 
Volume (vol) IEICE-118 
Number (no) no.456 
Page pp.25-30 
#Pages IEICE-6 
Date of Issue IEICE-DC-2019-02-20 


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