Paper Abstract and Keywords |
Presentation |
2019-02-27 16:45
Design of an FPGA-based Manycore Architecture with Selective Local/Global Memory Seiya Shirakuni (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-105 HWS2018-68 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA-based manycore architectures attract an increasing attention in order to realize high-performance embedded systems. Therefore, FPGA-based manycore architectures have been extensively proposed in several decades. This paper presents FPGA-based manycore architectures with selective local/grobal memory. We design and implement 33 core architectures which we proposed on an FPGA, and evaluate their performance. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
memory architecture / manycores / FPGA / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 118, no. 457, VLD2018-105, pp. 73-78, Feb. 2019. |
Paper # |
VLD2018-105 |
Date of Issue |
2019-02-20 (VLD, HWS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2018-105 HWS2018-68 |
Conference Information |
Committee |
HWS VLD |
Conference Date |
2019-02-27 - 2019-03-02 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa Ken Seinen Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Technology for System-on-Silicon, Hardware Security, etc. |
Paper Information |
Registration To |
VLD |
Conference Code |
2019-02-HWS-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Design of an FPGA-based Manycore Architecture with Selective Local/Global Memory |
Sub Title (in English) |
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memory architecture |
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manycores |
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FPGA |
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1st Author's Name |
Seiya Shirakuni |
1st Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
2nd Author's Name |
Ittetsu Taniguchi |
2nd Author's Affiliation |
Osaka University (Osaka Univ.) |
3rd Author's Name |
Hiroyuki Tomiyama |
3rd Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
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Speaker |
Author-1 |
Date Time |
2019-02-27 16:45:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2018-105, HWS2018-68 |
Volume (vol) |
vol.118 |
Number (no) |
no.457(VLD), no.458(HWS) |
Page |
pp.73-78 |
#Pages |
6 |
Date of Issue |
2019-02-20 (VLD, HWS) |
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