IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2019-02-27 13:40
State Assignment Method to Improve Transition Fault Coverage for Datapath
Masayoshi Yoshimura (Kyoto Sangyo Univ.), Yuki Takeuchi, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.) DC2018-78
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, it is indispensable to test in transition fault model due to timing defects increase along with complication and high speed of VLSI. However, the transition fault coverage tends to be lower than the stuck-at fault coverage due to untestable faults caused by the circuit structure. Therefore, there is a possibility of missing a potential failure for timing defects. Therefore, it is important to design-for-testability (DFT) to improve fault coverage in the transition fault model. In this paper, we show that transition fault coverages depend on state assignment to a controller in RTL netlist. We propose a QDT set which is an evaluation index on transition fault coverage for state assignment. Experimental results show that state assignment with high evaluation index has high transition fault coverages.
Keyword (in Japanese) (See Japanese page) 
(in English) transition fault / fault coverage / state assignment / QDT / / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 456, DC2018-78, pp. 43-48, Feb. 2019.
Paper # DC2018-78 
Date of Issue 2019-02-20 (DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF DC2018-78

Conference Information
Committee DC  
Conference Date 2019-02-27 - 2019-02-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Design and Test, etc. 
Paper Information
Registration To DC 
Conference Code 2019-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) State Assignment Method to Improve Transition Fault Coverage for Datapath 
Sub Title (in English)  
Keyword(1) transition fault  
Keyword(2) fault coverage  
Keyword(3) state assignment  
Keyword(4) QDT  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Masayoshi Yoshimura  
1st Author's Affiliation Kyoto Sangyo University (Kyoto Sangyo Univ.)
2nd Author's Name Yuki Takeuchi  
2nd Author's Affiliation Nihon University (Nihon Univ.)
3rd Author's Name Hiroshi Yamazaki  
3rd Author's Affiliation Nihon University (Nihon Univ.)
4th Author's Name Toshinori Hosokawa  
4th Author's Affiliation Nihon University (Nihon Univ.)
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker
Date Time 2019-02-27 13:40:00 
Presentation Time 25 
Registration for DC 
Paper # IEICE-DC2018-78 
Volume (vol) IEICE-118 
Number (no) no.456 
Page pp.43-48 
#Pages IEICE-6 
Date of Issue IEICE-DC-2019-02-20 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan