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| Presentation | 2019-02-27 15:20 Design Flow of Circuits with Multiple Supply Voltages for Power Reduction in General-Synchronous Framework Masataka Aoki, Yukihide Kohira (Univ. of Aizu)  VLD2018-102 HWS2018-65 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In general-synchronous framework (g-frame), in which a clock is not assumed to be distributed to all registers simultaneously, since delay may be used more efficiently than that in complete-synchronous framework (c-frame), it is expected to improve circuit performance. In recent integrated circuits, multiple voltages are supplied to the circuit with multiple power nets to reduce power consumption by setting an appropriate voltage for each circuit component. In this paper, we propose a design flow to realize high speed and low power consumption by combining g-frame and design with multiple supply voltages. In experiments, effectiveness of the proposed method is shown by comparing the circuits obtained by the proposed design flow with those in c-frame and g-frame. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | General-synchronous framework / multiple supply voltages / low power consumption / technology mapping / layout design / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 118, no. 457, VLD2018-102, pp. 55-60, Feb. 2019. | |
| Paper # | VLD2018-102 | |
| Date of Issue | 2019-02-20 (VLD, HWS) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2018-102 HWS2018-65 |
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| Conference Information | |
| Committee | HWS VLD |
| Conference Date | 2019-02-27 - 2019-03-02 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Ken Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon, Hardware Security, etc. |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2019-02-HWS-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design Flow of Circuits with Multiple Supply Voltages for Power Reduction in General-Synchronous Framework |
| Sub Title (in English) | |
| Keyword(1) | General-synchronous framework |
| Keyword(2) | multiple supply voltages |
| Keyword(3) | low power consumption |
| Keyword(4) | technology mapping |
| Keyword(5) | layout design |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Masataka Aoki |
| 1st Author's Affiliation | The University of Aizu (Univ. of Aizu) |
| 2nd Author's Name | Yukihide Kohira |
| 2nd Author's Affiliation | The University of Aizu (Univ. of Aizu) |
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| Speaker | Author-1 |
| Date Time | 2019-02-27 15:20:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2018-102, HWS2018-65 |
| Volume (vol) | vol.118 |
| Number (no) | no.457(VLD), no.458(HWS) |
| Page | pp.55-60 |
| #Pages | 6 |
| Date of Issue | 2019-02-20 (VLD, HWS) |
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