Paper Abstract and Keywords |
Presentation |
2019-02-27 12:40
Pattern Matching Based Detection of Wire Congestion from Source Code Description for High Level Synthesis Masato Tatsuoka, Mineo Kaneko (JAIST) VLD2018-96 HWS2018-59 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
When we use a high level synthesis (HLS) tool, the optimization of input code is necessary for obtaining an optimized RTL. In particular, routing congestion is difficult to resolve due to the lack of physical information in HLS phase. In our previous study, we proposed a high-level design flow that performs code optimization by detecting the congested part on the high-level synthesis input model using the source code compiler. In this report, we propose an extension of program dependence graph (PDG) for HLS code analysis and pattern matching on extended PDG as a method of detecting wire congestion. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
program dependence graph / pattern matching / LLVM / high level synthesis / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 118, no. 457, VLD2018-96, pp. 19-24, Feb. 2019. |
Paper # |
VLD2018-96 |
Date of Issue |
2019-02-20 (VLD, HWS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2018-96 HWS2018-59 |
Conference Information |
Committee |
HWS VLD |
Conference Date |
2019-02-27 - 2019-03-02 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa Ken Seinen Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Technology for System-on-Silicon, Hardware Security, etc. |
Paper Information |
Registration To |
VLD |
Conference Code |
2019-02-HWS-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Pattern Matching Based Detection of Wire Congestion from Source Code Description for High Level Synthesis |
Sub Title (in English) |
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program dependence graph |
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pattern matching |
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LLVM |
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high level synthesis |
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1st Author's Name |
Masato Tatsuoka |
1st Author's Affiliation |
Japan Advanced Institute of Science and Technology (JAIST) |
2nd Author's Name |
Mineo Kaneko |
2nd Author's Affiliation |
Japan Advanced Institute of Science and Technology (JAIST) |
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Speaker |
Author-1 |
Date Time |
2019-02-27 12:40:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2018-96, HWS2018-59 |
Volume (vol) |
vol.118 |
Number (no) |
no.457(VLD), no.458(HWS) |
Page |
pp.19-24 |
#Pages |
6 |
Date of Issue |
2019-02-20 (VLD, HWS) |
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