講演抄録/キーワード |
講演名 |
2019-02-27 11:45
An Efficient Approach to Recycled FPGA Detection Using WID Variation Modeling ○Foisal Ahmed・Michihiro Shintani・Michiko Inoue(NAIST) DC2018-77 |
抄録 |
(和) |
Recycled field programmable gate arrays (FPGAs) make a significant threat to mission critical systems due to their performance degradation and shorter lifetime caused by aging. In this paper, we propose a novel recycled FPGA detection method based on with-in die (WID) variation modeling. While fresh/recycled classification is carried out using measured frequencies from ring oscillators on FPGA in existing methods, the proposed method exploits model parameters extracted from the WID modeling. The model parameters simply and accurately represent the process variation of each FPGA, and thus the classification performs very well by the simple feature vector. Experimental results using circuit simulation demonstrate that the proposed method achieves 99.6% dimension reduction per FPGA chip with showing 96.0% detection accuracy using one-class support vector machine (SVM); while our silicon results on Xilinx Artix-7 FPGAs demonstrate the model parameters have good distance properties between fresh and aged. |
(英) |
Recycled field programmable gate arrays (FPGAs) make a significant threat to mission critical systems due to their performance degradation and shorter lifetime caused by aging. In this paper, we propose a novel recycled FPGA detection method based on with-in die (WID) variation modeling. While fresh/recycled classification is carried out using measured frequencies from ring oscillators on FPGA in existing methods, the proposed method exploits model parameters extracted from the WID modeling. The model parameters simply and accurately represent the process variation of each FPGA, and thus the classification performs very well by the simple feature vector. Experimental results using circuit simulation demonstrate that the proposed method achieves 99.6% dimension reduction per FPGA chip with showing 96.0% detection accuracy using one-class support vector machine (SVM); while our silicon results on Xilinx Artix-7 FPGAs demonstrate the model parameters have good distance properties between fresh and aged. |
キーワード |
(和) |
Recycled detection / Field programmable gate array (FPGA) / Process variation / With-in die process variation / Feature engineering / / / |
(英) |
Recycled detection / Field programmable gate array (FPGA) / Process variation / With-in die process variation / Feature engineering / / / |
文献情報 |
信学技報, vol. 118, no. 456, DC2018-77, pp. 37-42, 2019年2月. |
資料番号 |
DC2018-77 |
発行日 |
2019-02-20 (DC) |
ISSN |
Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
DC2018-77 |