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Paper Abstract and Keywords
Presentation 2019-01-30 11:20
An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults
Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo) VLD2018-74 CPSY2018-84 RECONF2018-48
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes an incremental ATPG method to deal with multiple stuck-at faults. In order to generate the test set for n multiple faults, only the additional test patterns for the undetected faults by the existing test patterns for n - 1 multiple faults are generated. Moreover, by introducing an efficient fault selection method, the size of the fault list to be dealt with isreduced drastically compared to the entire fault list of n multiple faults. Our experimental results on ISCAS benchmarks up to triple faults indicates that the proposed method can generate a compact test set to cover all the faults within an acceptable runtime.
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Reference Info. IEICE Tech. Rep., vol. 118, no. 430, VLD2018-74, pp. 13-18, Jan. 2019.
Paper # VLD2018-74 
Date of Issue 2019-01-23 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2018-74 CPSY2018-84 RECONF2018-48

Conference Information
Committee IPSJ-SLDM RECONF VLD CPSY IPSJ-ARC  
Conference Date 2019-01-30 - 2019-01-31 
Place (in Japanese) (See Japanese page) 
Place (in English) Raiosha, Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To VLD 
Conference Code 2019-01-SLDM-RECONF-VLD-CPSY-ARC 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults 
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1st Author's Name Peikun Wang  
1st Author's Affiliation The University of Tokyo (UTokyo)
2nd Author's Name Amir Masoud Gharehbaghi  
2nd Author's Affiliation The University of Tokyo (UTokyo)
3rd Author's Name Masahiro Fujita  
3rd Author's Affiliation The University of Tokyo (UTokyo)
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Speaker
Date Time 2019-01-30 11:20:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2018-74,IEICE-CPSY2018-84,IEICE-RECONF2018-48 
Volume (vol) IEICE-118 
Number (no) no.430(VLD), no.431(CPSY), no.432(RECONF) 
Page pp.13-18 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2019-01-23,IEICE-CPSY-2019-01-23,IEICE-RECONF-2019-01-23 


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