| IEICE Technical Committee Submission System Conference Paper's Information |
Online Proceedings [Sign in] Tech. Rep. Archives |
| Go Top Page | Go Previous | [Japanese] / [English] |
| Paper Abstract and Keywords | ||
| Presentation | 2019-01-23 13:30 Development of 30-GHz Datapath for Bit-Parallel, Gate-Level-Pipelined Rapid Single-Flux-Quantum Microprocessors Ikki Nagaoka (Nagoya Univ), Yuki Hatanaka (Mitsubishi Elec), Yuichi Matsui (Nagoya Univ), Koki Ishida (Kyushu Univ), Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita (Nagoya Univ), Takatsugu Ono, Koji Inoue (Kyushu Univ), Akira Fujimaki (Nagoya Univ)  SCE2018-30 Link to ES Tech. Rep. Archives: SCE2018-30 |
|
| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We have started development of high-throughput single-flux-quantum (SFQ) microprocessors with the aim of higher throughput performance beyond CMOS microprocessors. All of the demonstrated microprocessors based on SFQ logic employed bit-serial processing. The bit-serial processing leads to reduction of complexity and ease of design, but it limits throughput. It is necessary to introduce bit-parallel processing for obtaining higher throughput beyond CMOS microprocessors. We can expect significant improvement in the throughput performance by introducing bit-parallel processing and a gate-level pipelined structure, in which pipeline processing is performed logic gate by logic gate. In this study, to realize bit-parallel SFQ microprocessors, we designed and evaluated a datapath that was the most complex circuit in a microprocessor. We integrated an arithmetic logic unit (ALU) and a register file to increase the operation frequency. We confirmed correct operation of addition and subtraction instructions and part of write-back operation of the register file up to approximately 30GHz. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | SFQ circuit / Micorprocessor / Gate-level-pipeline / Bit-parallel processing / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 118, no. 415, SCE2018-30, pp. 29-34, Jan. 2019. | |
| Paper # | SCE2018-30 | |
| Date of Issue | 2019-01-16 (SCE) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SCE2018-30 Link to ES Tech. Rep. Archives: SCE2018-30 |
|
| Conference Information | |
| Committee | SCE |
| Conference Date | 2019-01-23 - 2019-01-23 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | SCE |
| Conference Code | 2019-01-SCE |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of 30-GHz Datapath for Bit-Parallel, Gate-Level-Pipelined Rapid Single-Flux-Quantum Microprocessors |
| Sub Title (in English) | |
| Keyword(1) | SFQ circuit |
| Keyword(2) | Micorprocessor |
| Keyword(3) | Gate-level-pipeline |
| Keyword(4) | Bit-parallel processing |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Ikki Nagaoka |
| 1st Author's Affiliation | Nagoya University (Nagoya Univ) |
| 2nd Author's Name | Yuki Hatanaka |
| 2nd Author's Affiliation | Mitsubishi Electric (Mitsubishi Elec) |
| 3rd Author's Name | Yuichi Matsui |
| 3rd Author's Affiliation | Nagoya University (Nagoya Univ) |
| 4th Author's Name | Koki Ishida |
| 4th Author's Affiliation | Kyushu University (Kyushu Univ) |
| 5th Author's Name | Masamitsu Tanaka |
| 5th Author's Affiliation | Nagoya University (Nagoya Univ) |
| 6th Author's Name | Kyosuke Sano |
| 6th Author's Affiliation | Nagoya University (Nagoya Univ) |
| 7th Author's Name | Taro Yamashita |
| 7th Author's Affiliation | Nagoya University (Nagoya Univ) |
| 8th Author's Name | Takatsugu Ono |
| 8th Author's Affiliation | Kyushu University (Kyushu Univ) |
| 9th Author's Name | Koji Inoue |
| 9th Author's Affiliation | Kyushu University (Kyushu Univ) |
| 10th Author's Name | Akira Fujimaki |
| 10th Author's Affiliation | Nagoya University (Nagoya Univ) |
| 11th Author's Name | |
| 11th Author's Affiliation | () |
| 12th Author's Name | |
| 12th Author's Affiliation | () |
| 13th Author's Name | |
| 13th Author's Affiliation | () |
| 14th Author's Name | |
| 14th Author's Affiliation | () |
| 15th Author's Name | |
| 15th Author's Affiliation | () |
| 16th Author's Name | |
| 16th Author's Affiliation | () |
| 17th Author's Name | |
| 17th Author's Affiliation | () |
| 18th Author's Name | |
| 18th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2019-01-23 13:30:00 |
| Presentation Time | 25 minutes |
| Registration for | SCE |
| Paper # | SCE2018-30 |
| Volume (vol) | vol.118 |
| Number (no) | no.415 |
| Page | pp.29-34 |
| #Pages | 6 |
| Date of Issue | 2019-01-16 (SCE) |
[Return to Top Page]