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| Presentation | 2018-12-07 09:50 A study on estimating the degradation of critical path delay using replica sensors Kunihiro Oshima, Son Bian, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.)  VLD2018-67 DC2018-53 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this paper, we propose a novel method to estimate the aging-induced timing degradation of logic circuits. In the proposed method, we first select a set of pMOS transistors that i) degrades significantly, and ii) are on the timing-critical paths in the target circuit design. Then, the selected transistors are replicated with the same input signals that feed original pMOS transistor. The timing degradations of the original transistors are then sensed through the changes in currents of the replicated transistors. In the experiment, we evaluate the sensitivity of the proposed sensor circuits through SPICE simulations. The simulation results show that the proposed method observe a 27.8% change in output current, much larger than the 2.39% current change reported in existing works. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Negative bias tempearature instability (NBTI) / aging sensor / detection of circuit lifespan / Subset Simulation / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 118, no. 334, VLD2018-67, pp. 195-200, Dec. 2018. | |
| Paper # | VLD2018-67 | |
| Date of Issue | 2018-11-28 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2018-67 DC2018-53 |
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| Conference Information | |
| Committee | VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM |
| Conference Date | 2018-12-05 - 2018-12-07 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Satellite Campus Hiroshima |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2018 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2018-12-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A study on estimating the degradation of critical path delay using replica sensors |
| Sub Title (in English) | |
| Keyword(1) | Negative bias tempearature instability (NBTI) |
| Keyword(2) | aging sensor |
| Keyword(3) | detection of circuit lifespan |
| Keyword(4) | Subset Simulation |
| Keyword(5) | |
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| 1st Author's Name | Kunihiro Oshima |
| 1st Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 2nd Author's Name | Son Bian |
| 2nd Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 3rd Author's Name | Masayuki Hiromoto |
| 3rd Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 4th Author's Name | Takashi Sato |
| 4th Author's Affiliation | Kyoto University (Kyoto Univ.) |
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| Speaker | Author-1 |
| Date Time | 2018-12-07 09:50:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2018-67, DC2018-53 |
| Volume (vol) | vol.118 |
| Number (no) | no.334(VLD), no.335(DC) |
| Page | pp.195-200 |
| #Pages | 6 |
| Date of Issue | 2018-11-28 (VLD, DC) |
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