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| Presentation | 2018-12-06 10:55 On the Generation of Random Capture Safe Test Vectors Using Neural Networks Sayuri Ochi, Kenichirou Misawa, Toshinori Hosokawa, Yukari Yamauchi, Masayuki Arai (Nihon Univ.)  VLD2018-51 DC2018-37 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Excessive capture power consumption at scan testing causes the excessive IR drop and it might cause test-induced yield loss. A low-capture-power test generation method for transition faults based on LOC using fault simulation was proposed to resolve the problem. The method mimics fault propagation path information for capture-safe test vectors which have low launch switching activity in the initial test sets. However, when the number of capture-safe test vectors is smaller, there exists faults which do not have any mimicked capture-safe test vectors. In this paper, we construct neural networks which are constituted from a test vector and state transition information of flip-flops as an input layer, circuit structure information as a middle layer, and capture-safe decision as an output layer. We learn low power properties of random test vectors using the neural network and consider an effective method of random capture-safe test vector generation using the neural network. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | low power testing / capture-safe test vectors / neural network / back propagation methods / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 118, no. 335, DC2018-37, pp. 89-94, Dec. 2018. | |
| Paper # | DC2018-37 | |
| Date of Issue | 2018-11-28 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2018-51 DC2018-37 |
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| Conference Information | |
| Committee | VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM |
| Conference Date | 2018-12-05 - 2018-12-07 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Satellite Campus Hiroshima |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2018 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2018-12-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On the Generation of Random Capture Safe Test Vectors Using Neural Networks |
| Sub Title (in English) | |
| Keyword(1) | low power testing |
| Keyword(2) | capture-safe test vectors |
| Keyword(3) | neural network |
| Keyword(4) | back propagation methods |
| Keyword(5) | |
| Keyword(6) | |
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| Keyword(8) | |
| 1st Author's Name | Sayuri Ochi |
| 1st Author's Affiliation | Nihon University (Nihon Univ.) |
| 2nd Author's Name | Kenichirou Misawa |
| 2nd Author's Affiliation | Nihon University (Nihon Univ.) |
| 3rd Author's Name | Toshinori Hosokawa |
| 3rd Author's Affiliation | Nihon University (Nihon Univ.) |
| 4th Author's Name | Yukari Yamauchi |
| 4th Author's Affiliation | Nihon University (Nihon Univ.) |
| 5th Author's Name | Masayuki Arai |
| 5th Author's Affiliation | Nihon University (Nihon Univ.) |
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| Speaker | Author-1 |
| Date Time | 2018-12-06 10:55:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | VLD2018-51, DC2018-37 |
| Volume (vol) | vol.118 |
| Number (no) | no.334(VLD), no.335(DC) |
| Page | pp.89-94 |
| #Pages | 6 |
| Date of Issue | 2018-11-28 (VLD, DC) |
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