Paper Abstract and Keywords |
Presentation |
2018-12-06 09:25
Transparent Acceleration Method for Network Function Virtualization Using FPGA Yoshikazu Watanabe, Yuki Kobayashi, Takashi Takenaka, Baba Hiroshi (NEC) RECONF2018-38 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Network Function Virtualization (NFV) is becoming a new networking architecture for telecom carriers.
While NFV realizes network functions with software and commercial off the shelf (COTS) servers instead of dedicated hardware,
the performance of the software could be bottleneck.
This paper proposes a method for accelerating NFV application with FPGA transparently.
The method leverages a CPU-FPGA tightly coupled architecture.
We report the result of implementation and evaluation of vCPE acceleration on a CPU+FPGA evaluation platform. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / Network Function Virtualization / NFV / CPU-FPGA Tightly Coupled Architecture / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 118, no. 340, RECONF2018-38, pp. 21-26, Dec. 2018. |
Paper # |
RECONF2018-38 |
Date of Issue |
2018-11-28 (RECONF) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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RECONF2018-38 |
Conference Information |
Committee |
VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM |
Conference Date |
2018-12-05 - 2018-12-07 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Satellite Campus Hiroshima |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2018 -New Field of VLSI Design- |
Paper Information |
Registration To |
RECONF |
Conference Code |
2018-12-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Transparent Acceleration Method for Network Function Virtualization Using FPGA |
Sub Title (in English) |
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Keyword(1) |
FPGA |
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Network Function Virtualization |
Keyword(3) |
NFV |
Keyword(4) |
CPU-FPGA Tightly Coupled Architecture |
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1st Author's Name |
Yoshikazu Watanabe |
1st Author's Affiliation |
NEC Corporation (NEC) |
2nd Author's Name |
Yuki Kobayashi |
2nd Author's Affiliation |
NEC Corporation (NEC) |
3rd Author's Name |
Takashi Takenaka |
3rd Author's Affiliation |
NEC Corporation (NEC) |
4th Author's Name |
Baba Hiroshi |
4th Author's Affiliation |
NEC Corporation (NEC) |
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Speaker |
Author-1 |
Date Time |
2018-12-06 09:25:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
RECONF2018-38 |
Volume (vol) |
vol.118 |
Number (no) |
no.340 |
Page |
pp.21-26 |
#Pages |
6 |
Date of Issue |
2018-11-28 (RECONF) |