Paper Abstract and Keywords |
Presentation |
2018-12-05 09:55
Development of Software/Hardware Cooperative System for Radiosity Method using High-Level Synthesis with an FPGA Kotaro Tamura, Tetsu Narumi (UEC univ.) RECONF2018-34 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The calculation cost of a Radiosity method is huge, since it takes into account the global illumination to produce realistic images. Recently, an FPGA accelerator can be implemented using high level synthesis. However, such arithmetic units are difficult to optimize when high level synthesis is used. In this paper, we developed a heterogeneous system using Zynq SoC to accelerate the Radiosity method, and evaluated the optimization method. Several optimization methods with SDSoC greatly reduced hardware resource and latency without losing accuracy. However, we need to further analyze the bottleneck since the calculation speed of the FPGA is slower than that of the CPU alone. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / High Level Synthesis / SDSoC / 3DCG / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 118, no. 340, RECONF2018-34, pp. 1-6, Dec. 2018. |
Paper # |
RECONF2018-34 |
Date of Issue |
2018-11-28 (RECONF) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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RECONF2018-34 |
Conference Information |
Committee |
VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM |
Conference Date |
2018-12-05 - 2018-12-07 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Satellite Campus Hiroshima |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2018 -New Field of VLSI Design- |
Paper Information |
Registration To |
RECONF |
Conference Code |
2018-12-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Development of Software/Hardware Cooperative System for Radiosity Method using High-Level Synthesis with an FPGA |
Sub Title (in English) |
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FPGA |
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High Level Synthesis |
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SDSoC |
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3DCG |
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1st Author's Name |
Kotaro Tamura |
1st Author's Affiliation |
The University of Electro-Communications (UEC univ.) |
2nd Author's Name |
Tetsu Narumi |
2nd Author's Affiliation |
The University of Electro-Communications (UEC univ.) |
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Speaker |
Author-1 |
Date Time |
2018-12-05 09:55:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
RECONF2018-34 |
Volume (vol) |
vol.118 |
Number (no) |
no.340 |
Page |
pp.1-6 |
#Pages |
6 |
Date of Issue |
2018-11-28 (RECONF) |
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