Paper Abstract and Keywords |
Presentation |
2018-11-15 13:30
Phase Control Method for Subsampling PLL by Varying Phase and Frequency of Clock Signal of S/H Circuit Osamu Wada, Hiroyuki Mizutani, Kenichi Tajima (Mitsubishi Electric Corp.) MW2018-97 Link to ES Tech. Rep. Archives: MW2018-97 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A phase control method of PLL that generates a LO signal was reported as controlling a phase difference between transmitted signals in an APAA system. In addition, low phase noise performance is required for the PLL in order to improve radar performance and communication quality in the APAA system. In this paper, phase control method for subsampling PLL by varying phase and frequency of clock signal of S/H circuit is proposed. In the proposed method, a phase of an output signal of the subsampling PLL is expressed by the product of a phase of the clock signal and a frequency ratio of the clock signal and the output signal. The proposed method enables the phase control by varying the phase and frequency of the clock signal. Experimental results show the desired phase control performance. A measured maximum phase difference between calculated and experimental results was 2.13degree p-p. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Subsampling PLL / Phase control / S/H circuit / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 118, no. 308, MW2018-97, pp. 31-34, Nov. 2018. |
Paper # |
MW2018-97 |
Date of Issue |
2018-11-08 (MW) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
MW2018-97 Link to ES Tech. Rep. Archives: MW2018-97 |
Conference Information |
Committee |
MW |
Conference Date |
2018-11-15 - 2018-11-16 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Fukue Cultural Hall |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Microwave Technologies |
Paper Information |
Registration To |
MW |
Conference Code |
2018-11-MW |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Phase Control Method for Subsampling PLL by Varying Phase and Frequency of Clock Signal of S/H Circuit |
Sub Title (in English) |
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Keyword(1) |
Subsampling PLL |
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Phase control |
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S/H circuit |
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1st Author's Name |
Osamu Wada |
1st Author's Affiliation |
Mitsubishi Electric Corporation (Mitsubishi Electric Corp.) |
2nd Author's Name |
Hiroyuki Mizutani |
2nd Author's Affiliation |
Mitsubishi Electric Corporation (Mitsubishi Electric Corp.) |
3rd Author's Name |
Kenichi Tajima |
3rd Author's Affiliation |
Mitsubishi Electric Corporation (Mitsubishi Electric Corp.) |
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Speaker |
Author-1 |
Date Time |
2018-11-15 13:30:00 |
Presentation Time |
25 minutes |
Registration for |
MW |
Paper # |
MW2018-97 |
Volume (vol) |
vol.118 |
Number (no) |
no.308 |
Page |
pp.31-34 |
#Pages |
4 |
Date of Issue |
2018-11-08 (MW) |