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Paper Abstract and Keywords
Presentation 2018-11-08 11:20
[Invited Talk] Proposal and device design of tunneling field effect transistor with oxide semiconductor and group-IV semiconductor
Kimihiko Kato, Hiroaki Matsui, Hitoshi Tabata, Mitsuru Takenaka, Shinichi Takagi (Univ. Tokyo) SDM2018-66 Link to ES Tech. Rep. Archives: SDM2018-66
Abstract (in Japanese) (See Japanese page) 
(in English) A novel bilayer tunneling field effect transistor (TFET) employing an attractive material combination of oxide-semiconductors and group-IV-semiconductors with type-II energy band alignment is proposed, in this study. Based on TCAD simulation and experimental demonstration, high potential of the proposed bilayer TFET as a steep-slope device and impacts of key device parameters such as energy band alignment and impurity concentration on electrical performance of the bilayer TFET have been widely studied. Also, influences of channel thickness non-uniformity and interface state, which could be critical issues for realistic device fabrication, have been investigated. This comprehensive understanding leads a clear guideline for device design of high-performance bilayer TFETs.
Keyword (in Japanese) (See Japanese page) 
(in English) Tunneling transistor / Steep-slope / Oxide semiconductor / Group-IV semiconductor / / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 291, SDM2018-66, pp. 11-16, Nov. 2018.
Paper # SDM2018-66 
Date of Issue 2018-11-01 (SDM) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
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Download PDF SDM2018-66 Link to ES Tech. Rep. Archives: SDM2018-66

Conference Information
Committee SDM  
Conference Date 2018-11-08 - 2018-11-09 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Process, Device, Circuit simulation, etc. 
Paper Information
Registration To SDM 
Conference Code 2018-11-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Proposal and device design of tunneling field effect transistor with oxide semiconductor and group-IV semiconductor 
Sub Title (in English)  
Keyword(1) Tunneling transistor  
Keyword(2) Steep-slope  
Keyword(3) Oxide semiconductor  
Keyword(4) Group-IV semiconductor  
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1st Author's Name Kimihiko Kato  
1st Author's Affiliation The University of Tokyo (Univ. Tokyo)
2nd Author's Name Hiroaki Matsui  
2nd Author's Affiliation The University of Tokyo (Univ. Tokyo)
3rd Author's Name Hitoshi Tabata  
3rd Author's Affiliation The University of Tokyo (Univ. Tokyo)
4th Author's Name Mitsuru Takenaka  
4th Author's Affiliation The University of Tokyo (Univ. Tokyo)
5th Author's Name Shinichi Takagi  
5th Author's Affiliation The University of Tokyo (Univ. Tokyo)
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Speaker
Date Time 2018-11-08 11:20:00 
Presentation Time 60 
Registration for SDM 
Paper # IEICE-SDM2018-66 
Volume (vol) IEICE-118 
Number (no) no.291 
Page pp.11-16 
#Pages IEICE-6 
Date of Issue IEICE-SDM-2018-11-01 


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