IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2018-10-19 10:20
An efficient variable-gain homotopy method for finding DC operating points of transistor circuits
Kiyotaka Yamamura, Takumi Shimada (Chuo Univ.) CAS2018-51 NLP2018-86
Abstract (in Japanese) (See Japanese page) 
(in English) Homotopy methods are known to be effective methods for finding DC operating points of nonlinear circuits with the theoretical guarantee of global convergence There are several types of homotopy methods; as one of the most efficient methods for solving bipolar transistor circuits, the variable-gain homotopy (VGH) method is well-known. In this paper, we propose an efficient VGH method where a more effective linear function is used in the homotopy function. By numerical examples, it is shown that the proposed method is more efficient than the conventional VGH method. It is also shown that the proposed method is globally convergent for modified nodal equations and can be implemented in SPICE easily without writing complicated programs.
Keyword (in Japanese) (See Japanese page) 
(in English) circuit simulation / DC operating point analysis / nonlinear circuit / non-convergence problem / homotopy method / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 243, NLP2018-86, pp. 75-79, Oct. 2018.
Paper # NLP2018-86 
Date of Issue 2018-10-11 (CAS, NLP) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CAS2018-51 NLP2018-86

Conference Information
Committee CAS NLP  
Conference Date 2018-10-18 - 2018-10-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Tohoku Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Mathematical modeling, numerical simulation etc. 
Paper Information
Registration To NLP 
Conference Code 2018-10-CAS-NLP 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An efficient variable-gain homotopy method for finding DC operating points of transistor circuits 
Sub Title (in English)  
Keyword(1) circuit simulation  
Keyword(2) DC operating point analysis  
Keyword(3) nonlinear circuit  
Keyword(4) non-convergence problem  
Keyword(5) homotopy method  
1st Author's Name Kiyotaka Yamamura  
1st Author's Affiliation Chuo University (Chuo Univ.)
2nd Author's Name Takumi Shimada  
2nd Author's Affiliation Chuo University (Chuo Univ.)
3rd Author's Name  
3rd Author's Affiliation ()
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Date Time 2018-10-19 10:20:00 
Presentation Time 25 
Registration for NLP 
Paper # IEICE-CAS2018-51,IEICE-NLP2018-86 
Volume (vol) IEICE-118 
Number (no) no.242(CAS), no.243(NLP) 
Page pp.75-79 
#Pages IEICE-5 
Date of Issue IEICE-CAS-2018-10-11,IEICE-NLP-2018-10-11 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan