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Paper Abstract and Keywords
Presentation 2018-07-31 14:30
Reduction of Indirect Addressing in Parallel-Program Generation for Improving Memory Efficiency on Vector Processor
Yujiro Ishida, Masao Okita, Kenichi Hagihara, Fumihiko Ino (Osaka Univ.) CPSY2018-20
Abstract (in Japanese) (See Japanese page) 
(in English) We discuss automatic code generation of a vectorizable program from a large-scale mathematical model. Indirect addressing of array elements is useful to vectorize loops that include irregular memory access patterns. However, vectorizing compilers translate indirect addressing into gather/scatter instructions independent of data placement, resulting in a possible performance bottleneck for memory-intensive programs. In this report, we propose a method that replaces redundant indirect addressing with direct addressing by analyzing access patterns during code generation. Furthermore, out method increase access patterns to be writable in a direct addressing manner by enhancing sequential access. Experimental results on SX-ACE demonstrate that the proposed method accelerates a biophysical simulation program including more than 30 million equations by a factor of 1.4.
Keyword (in Japanese) (See Japanese page) 
(in English) SX-ACE / Data placement / Auto-vectorization / DSL / / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 165, CPSY2018-20, pp. 115-120, July 2018.
Paper # CPSY2018-20 
Date of Issue 2018-07-23 (CPSY) 
ISSN Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2018-20

Conference Information
Committee CPSY DC IPSJ-ARC  
Conference Date 2018-07-30 - 2018-08-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Kumamoto City International Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Parallel, Distributed and Cooperative Processing Systems and Dependable Computing 
Paper Information
Registration To CPSY 
Conference Code 2018-07-CPSY-DC-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Reduction of Indirect Addressing in Parallel-Program Generation for Improving Memory Efficiency on Vector Processor 
Sub Title (in English)  
Keyword(1) SX-ACE  
Keyword(2) Data placement  
Keyword(3) Auto-vectorization  
Keyword(4) DSL  
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1st Author's Name Yujiro Ishida  
1st Author's Affiliation Osaka University (Osaka Univ.)
2nd Author's Name Masao Okita  
2nd Author's Affiliation Osaka University (Osaka Univ.)
3rd Author's Name Kenichi Hagihara  
3rd Author's Affiliation Osaka University (Osaka Univ.)
4th Author's Name Fumihiko Ino  
4th Author's Affiliation Osaka University (Osaka Univ.)
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Speaker Author-1 
Date Time 2018-07-31 14:30:00 
Presentation Time 30 minutes 
Registration for CPSY 
Paper # CPSY2018-20 
Volume (vol) vol.118 
Number (no) no.165 
Page pp.115-120 
#Pages
Date of Issue 2018-07-23 (CPSY) 


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