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Paper Abstract and Keywords
Presentation 2018-07-30 14:30
Proposition and Implementation of RISC-V Processor with Data path extension for 10G Ethernet
Yosuke Yanai, Takeshi Matsuya, Yohei Kuga, Tokusashi Yuta, Jun Murai (Keio Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a processor with 1024 bit wide data path for packet processing. A software packet processing environment typified by Intel DPDK realizes high-speed packet processing in a 10 G / 100 G Ethernet environment using a high clock and multi-core CPU. In this proposed function extension, we aim to realize high-speed packet processing with single core and low clock by connecting 1024 bit wide data path that exchanges data with Ethernet PHY to CPU. In this paper, we implemented 32bit RISC-V processor and extension of our proposed method using FPGA. In the evaluation, we confirmed that it is possible to process packets with throughput of 99.1% with respect to the line rate of 10 G Ethernet while processing part of routing.
Keyword (in Japanese) (See Japanese page) 
(in English) RISC-V / Processor / Architecture / Packet processing / Network / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 165, CPSY2018-15, pp. 33-38, July 2018.
Paper # CPSY2018-15 
Date of Issue 2018-07-23 (CPSY) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380

Conference Information
Committee CPSY DC IPSJ-ARC  
Conference Date 2018-07-30 - 2018-08-01 
Place (in Japanese) (See Japanese page) 
Place (in English) Kumamoto City International Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Parallel, Distributed and Cooperative Processing Systems and Dependable Computing 
Paper Information
Registration To CPSY 
Conference Code 2018-07-CPSY-DC-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Proposition and Implementation of RISC-V Processor with Data path extension for 10G Ethernet 
Sub Title (in English)  
Keyword(1) RISC-V  
Keyword(2) Processor  
Keyword(3) Architecture  
Keyword(4) Packet processing  
Keyword(5) Network  
1st Author's Name Yosuke Yanai  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Takeshi Matsuya  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Yohei Kuga  
3rd Author's Affiliation Keio University (Keio Univ.)
4th Author's Name Tokusashi Yuta  
4th Author's Affiliation Keio University (Keio Univ.)
5th Author's Name Jun Murai  
5th Author's Affiliation Keio University (Keio Univ.)
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Date Time 2018-07-30 14:30:00 
Presentation Time 30 
Registration for CPSY 
Paper # IEICE-CPSY2018-15 
Volume (vol) IEICE-118 
Number (no) no.165 
Page pp.33-38 
#Pages IEICE-6 
Date of Issue IEICE-CPSY-2018-07-23 

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