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Paper Abstract and Keywords
Presentation 2018-06-14 16:35
Area Efficient Multiply-Accumulate Circuit Using Stochastic Computing for Neural Network Hardware
Kenta Nagura, Masayuki Hiromoto, Takashi Sato (Kyoto Univ)
Abstract (in Japanese) (See Japanese page) 
(in English) Neural network, which is an accurate and general-purpose machine learning method, is attracting greater attention in recent years. Due to the heavy computational load required in both learning and inference, the circuit area and power consumption become large when the neural network is implemented on a hardware. To improve calculation efficiency, we propose to apply stochastic computing (SC) in which the numerical numbers are represented by the number of 1's in a bit sequence. In this paper, we propose a new multiply-accumulate circuit (MAC) using SC, which is a heavily repeated calculation in neural network algorithms. Through experiments, we show the proposed MAC circuit greatly improves the accuracy of the calculation compared with an existing MAC circuit using SC of equal circuit area and power.
Keyword (in Japanese) (See Japanese page) 
(in English) neural network / multiply-accumulate circuit / image recognition / stochastic computing / / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 83, VLD2018-18, pp. 81-86, June 2018.
Paper # VLD2018-18 
Date of Issue 2018-06-07 (CAS, VLD, SIP, MSS) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380

Conference Information
Committee CAS SIP MSS VLD  
Conference Date 2018-06-14 - 2018-06-15 
Place (in Japanese) (See Japanese page) 
Place (in English) Hokkaido Univ. (Frontier Research in Applied Sciences Build.) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System and Signal Processing, etc 
Paper Information
Registration To VLD 
Conference Code 2018-06-CAS-SIP-MSS-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Area Efficient Multiply-Accumulate Circuit Using Stochastic Computing for Neural Network Hardware 
Sub Title (in English)  
Keyword(1) neural network  
Keyword(2) multiply-accumulate circuit  
Keyword(3) image recognition  
Keyword(4) stochastic computing  
1st Author's Name Kenta Nagura  
1st Author's Affiliation Kyoto University (Kyoto Univ)
2nd Author's Name Masayuki Hiromoto  
2nd Author's Affiliation Kyoto University (Kyoto Univ)
3rd Author's Name Takashi Sato  
3rd Author's Affiliation Kyoto University (Kyoto Univ)
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Date Time 2018-06-14 16:35:00 
Presentation Time 20 
Registration for VLD 
Paper # IEICE-CAS2018-15,IEICE-VLD2018-18,IEICE-SIP2018-35,IEICE-MSS2018-15 
Volume (vol) IEICE-118 
Number (no) no.82(CAS), no.83(VLD), no.84(SIP), no.85(MSS) 
Page pp.81-86 
#Pages IEICE-6 
Date of Issue IEICE-CAS-2018-06-07,IEICE-VLD-2018-06-07,IEICE-SIP-2018-06-07,IEICE-MSS-2018-06-07 

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