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Paper Abstract and Keywords
Presentation 2018-04-13 13:55
Energy Evaluation of FPGA Pairing Implementation with Pipeline Modular Multiplier
Yusuke Nagahama, Daisuke Fujimoto, Junichi Sakamoto, Tsutomu Matsumoto (YNU) HWS2018-5
Abstract (in Japanese) (See Japanese page) 
(in English) Energy consumption and latency are important features of dedicated hardware bilinear pairing calculators. However published papers on FPGA implementation of such dedicated hardware rarely discuss energy evaluation. In this paper we evaluate the energy consumption of the brand-new pairing calculator which adopts pipeline type modular multipliers.
The evaluation is carried out using the VCU 118 board equipped with Xilinx’s Virtex UltraScale + FPGA. In addition, we compare the latency and energy of the previous implementation in the literature with compensation to the same generation FPGA as Virtex UltraScale +.
Keyword (in Japanese) (See Japanese page) 
(in English) Hardware architecture / Finite field multiplier / Montgomery multiplication / Pairing encryption / Energy Evaluation / / /  
Reference Info. IEICE Tech. Rep., vol. 118, no. 3, HWS2018-5, pp. 23-28, April 2018.
Paper # HWS2018-5 
Date of Issue 2018-04-06 (HWS) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee HWS  
Conference Date 2018-04-13 - 2018-04-13 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To HWS 
Conference Code 2018-04-HWS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Energy Evaluation of FPGA Pairing Implementation with Pipeline Modular Multiplier 
Sub Title (in English)  
Keyword(1) Hardware architecture  
Keyword(2) Finite field multiplier  
Keyword(3) Montgomery multiplication  
Keyword(4) Pairing encryption  
Keyword(5) Energy Evaluation  
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Keyword(7)  
Keyword(8)  
1st Author's Name Yusuke Nagahama  
1st Author's Affiliation Yokohama National University (YNU)
2nd Author's Name Daisuke Fujimoto  
2nd Author's Affiliation Yokohama National University (YNU)
3rd Author's Name Junichi Sakamoto  
3rd Author's Affiliation Yokohama National University (YNU)
4th Author's Name Tsutomu Matsumoto  
4th Author's Affiliation Yokohama National University (YNU)
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Speaker
Date Time 2018-04-13 13:55:00 
Presentation Time 25 
Registration for HWS 
Paper # IEICE-HWS2018-5 
Volume (vol) IEICE-118 
Number (no) no.3 
Page pp.23-28 
#Pages IEICE-6 
Date of Issue IEICE-HWS-2018-04-06 


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