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Paper Abstract and Keywords
Presentation 2018-03-02 10:30
Implementation of Reconfigurable Accelerator Cool Mega-Array Using MTJ-based Nonvolatile Flip-Flop Enabling to Verify Stored Data
Junya Akaike, Kimiyoshi Usami, Masaru Kudo (SIT), Hideharu Amano, Takeharu Ikezoe (Keio Univ.), Keizo Hiraga, Yusuke Shuto, Kojiro Yagami (Sony SS) VLD2017-122
Abstract (in Japanese) (See Japanese page) 
(in English) As a method of reducing the power consumption of the flip-flop circuit, there is a nonvolatile flip-flop (NVFF) that enables power gating by using magnetic tunnel junction (MTJ). Furthermore, the NVFF that realizes store energy reduction by enabling to verify stored data has been proposed. However, the control to verify is complicated, and it requires to change the operation depending on each application. In this paper, we propose a method and circuit structure enabling the NVFF control by assembly instructions of a reconfigurable accelerator Cool Mega-Array (CMA) using the NVFF enabling to verify. We show the simulation results of the energy consumption when operating the application.
Keyword (in Japanese) (See Japanese page) 
(in English) Low Energy Consumption / Power-Gating / MTJ / Flip-Flop / Cool Mega-Array / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 455, VLD2017-122, pp. 199-204, Feb. 2018.
Paper # VLD2017-122 
Date of Issue 2018-02-21 (VLD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2017-122

Conference Information
Committee VLD HWS  
Conference Date 2018-02-28 - 2018-03-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2018-02-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation of Reconfigurable Accelerator Cool Mega-Array Using MTJ-based Nonvolatile Flip-Flop Enabling to Verify Stored Data 
Sub Title (in English)  
Keyword(1) Low Energy Consumption  
Keyword(2) Power-Gating  
Keyword(3) MTJ  
Keyword(4) Flip-Flop  
Keyword(5) Cool Mega-Array  
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Keyword(7)  
Keyword(8)  
1st Author's Name Junya Akaike  
1st Author's Affiliation Shibaura Institute of Technology (SIT)
2nd Author's Name Kimiyoshi Usami  
2nd Author's Affiliation Shibaura Institute of Technology (SIT)
3rd Author's Name Masaru Kudo  
3rd Author's Affiliation Shibaura Institute of Technology (SIT)
4th Author's Name Hideharu Amano  
4th Author's Affiliation Keio University (Keio Univ.)
5th Author's Name Takeharu Ikezoe  
5th Author's Affiliation Keio University (Keio Univ.)
6th Author's Name Keizo Hiraga  
6th Author's Affiliation Sony Semiconductor Solutions Corporation (Sony SS)
7th Author's Name Yusuke Shuto  
7th Author's Affiliation Sony Semiconductor Solutions Corporation (Sony SS)
8th Author's Name Kojiro Yagami  
8th Author's Affiliation Sony Semiconductor Solutions Corporation (Sony SS)
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Speaker
Date Time 2018-03-02 10:30:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2017-122 
Volume (vol) IEICE-117 
Number (no) no.455 
Page pp.199-204 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2018-02-21 


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