Paper Abstract and Keywords |
Presentation |
2018-03-01 13:25
A Study on Energy Optimization for Asynchronous RTL Models with Bundled-data Implementation Shogo Semba, Hiroshi Saito (UoA) VLD2017-111 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this work, we study two energy optimization methods for asynchronous RTL models with bundled-data implementation. The first is the use of the maximum delay constraints for paths. The second is the reduction of power consumption by fixing select signals for multiplexers. In the experiment, we apply the two methods for two benchmark circuits. Then, we synthesize the logic circuits for these circuits and evaluate the energy consumption. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Asynchronous circuits / Logic design / Energy optimization / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 117, no. 455, VLD2017-111, pp. 133-138, Feb. 2018. |
Paper # |
VLD2017-111 |
Date of Issue |
2018-02-21 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2017-111 |
Conference Information |
Committee |
VLD HWS |
Conference Date |
2018-02-28 - 2018-03-02 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa Seinen Kaikan |
Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
VLD |
Conference Code |
2018-02-VLD-HWS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Study on Energy Optimization for Asynchronous RTL Models with Bundled-data Implementation |
Sub Title (in English) |
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Asynchronous circuits |
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Logic design |
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Energy optimization |
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1st Author's Name |
Shogo Semba |
1st Author's Affiliation |
The University of Aizu (UoA) |
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Hiroshi Saito |
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The University of Aizu (UoA) |
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Speaker |
Author-1 |
Date Time |
2018-03-01 13:25:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2017-111 |
Volume (vol) |
vol.117 |
Number (no) |
no.455 |
Page |
pp.133-138 |
#Pages |
6 |
Date of Issue |
2018-02-21 (VLD) |
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