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| Presentation | 2018-02-28 16:30 Reconfiguration for Fault Tolerant FPGA Considering Incremental Multiple Faults Cheng Ma, Mineo Kaneko (JAIST)  VLD2017-101 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The report treats the reconfiguration-based fault-tolerance for FPGA applications, and proposes a method of finding a chained replacement of frames in FPGA. In order to realize a longer working time of FPGA application, we have taken the timing slack into account in reconfiguration phase, and have developed a performance-aware chained replacement exploration under an incremental multiple fault model. The experimental result shows the improvement of working time (in terms of the number of incremental faults recovered) compared with the conventional shortest-path-based chained replacement. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FPGA / fault-tolerant / reconfiguration / hard-error / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 117, no. 455, VLD2017-101, pp. 73-78, Feb. 2018. | |
| Paper # | VLD2017-101 | |
| Date of Issue | 2018-02-21 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2017-101 |
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| Conference Information | |
| Committee | VLD HWS |
| Conference Date | 2018-02-28 - 2018-03-02 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2018-02-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Reconfiguration for Fault Tolerant FPGA Considering Incremental Multiple Faults |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | fault-tolerant |
| Keyword(3) | reconfiguration |
| Keyword(4) | hard-error |
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| 1st Author's Name | Cheng Ma |
| 1st Author's Affiliation | Japan Advanced Institute of Science and Technology (JAIST) |
| 2nd Author's Name | Mineo Kaneko |
| 2nd Author's Affiliation | Japan Advanced Institute of Science and Technology (JAIST) |
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| Speaker | Author-1 |
| Date Time | 2018-02-28 16:30:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2017-101 |
| Volume (vol) | vol.117 |
| Number (no) | no.455 |
| Page | pp.73-78 |
| #Pages | 6 |
| Date of Issue | 2018-02-21 (VLD) |
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