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Paper Abstract and Keywords
Presentation 2018-02-20 11:40
A test generation method based on k-cycle testing for finite state machines
Yuya Kinoshita, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2017-81
Abstract (in Japanese) (See Japanese page) 
(in English) Recent advances in semiconductor technologies have resulted in VLSI circuit density and complexity. As a result, efficient test generation methods are required. Since the test generation using the time expansion model focuses only on the circuit structure, it is difficult to achieve high fault coverage. In this paper, we propose Time Expansion Model with Initial State constraints (TEMIS) for the controller circuits and its test generation method. Experimental results show that our proposed method achieves 100% of fault coverage for a lot of controller circuits and they could gain higher fault coverage than TetraMax test generation using a time expansion model.
Keyword (in Japanese) (See Japanese page) 
(in English) sequential test generation / finite state machines / k-cycle testing / register transfer level / controllers / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 444, DC2017-81, pp. 25-30, Feb. 2018.
Paper # DC2017-81 
Date of Issue 2018-02-13 (DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2018-02-20 - 2018-02-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Design and Test, etc. 
Paper Information
Registration To DC 
Conference Code 2018-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A test generation method based on k-cycle testing for finite state machines 
Sub Title (in English)  
Keyword(1) sequential test generation  
Keyword(2) finite state machines  
Keyword(3) k-cycle testing  
Keyword(4) register transfer level  
Keyword(5) controllers  
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1st Author's Name Yuya Kinoshita  
1st Author's Affiliation Nihon University (Nihon Univ.)
2nd Author's Name Toshinori Hosokawa  
2nd Author's Affiliation Nihon University (Nihon Univ.)
3rd Author's Name Hideo Fujiwara  
3rd Author's Affiliation Osaka Gakuin University (Osaka Gakuin Univ.)
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Speaker
Date Time 2018-02-20 11:40:00 
Presentation Time 25 
Registration for DC 
Paper # IEICE-DC2017-81 
Volume (vol) IEICE-117 
Number (no) no.444 
Page pp.25-30 
#Pages IEICE-6 
Date of Issue IEICE-DC-2018-02-13 


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