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Paper Abstract and Keywords
Presentation 2018-02-20 09:30
Note on Weighted Fault Coverage for Two-Pattern Tests
Masayuki Arai (Nihon Univ.), Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2017-77
Abstract (in Japanese) (See Japanese page) 
(in English) hrinking feature size and higher integration on semiconductor device manufacturing technology bring a problem of the gap between the defect level estimated at the design stage from the reported one for fabricated devices. As one possible strategy to accurately estimate the defect level, authors have proposed weighted bridge/open fault coverage estimation, as well as test generation algorithms based on the weighted fault coverage. Previous work has only taken static fault models into account. In this study we introduce a fault model considering static and dynamic behavior of a defect, assuming that a part of behavior of a defect can only be observed as rise/fall delay. Targeting test pattern sets consisting of 2-pattern tests, we calculate weighted bridge/open fault coverage, and compare with conventional fault coverages based on delay and static fault models.
Keyword (in Japanese) (See Japanese page) 
(in English) weighted fault coverage / critical area / bridge fault / open fault / delay fault / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 444, DC2017-77, pp. 1-6, Feb. 2018.
Paper # DC2017-77 
Date of Issue 2018-02-13 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2018-02-20 - 2018-02-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Design and Test, etc. 
Paper Information
Registration To DC 
Conference Code 2018-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Note on Weighted Fault Coverage for Two-Pattern Tests 
Sub Title (in English)  
Keyword(1) weighted fault coverage  
Keyword(2) critical area  
Keyword(3) bridge fault  
Keyword(4) open fault  
Keyword(5) delay fault  
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1st Author's Name Masayuki Arai  
1st Author's Affiliation Nihon University (Nihon Univ.)
2nd Author's Name Kazuhiko Iwasaki  
2nd Author's Affiliation Tokyo Metropolitan University (Tokyo Metro. Univ.)
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Speaker Author-1 
Date Time 2018-02-20 09:30:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2017-77 
Volume (vol) vol.117 
Number (no) no.444 
Page pp.1-6 
#Pages
Date of Issue 2018-02-13 (DC) 


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