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Paper Abstract and Keywords
Presentation 2018-02-20 10:35
Reduction of Wire Length by Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) DC2017-79
Abstract (in Japanese) (See Japanese page) 
(in English) TSV attracts attention as a new implementation method of interconnects between dies in 3DICs.
However, faulty TSVs may cause small delay faults because of defects in TSVs such as voids and pinholes during the manufacturing process.
We have been proposed a DFT(Design-For-Testability) method for TSVs using a boundary scan circuit with embedded TDC(TDCBS).
We proposed the design method for reducing variation of additional delay by reordering delay elements.
However, in this method, the wire for forming a loop becomes long compared with other wires.
In this paper, we present the design method for reducing the wire length of the feedback wire by reordering delay elements under consideration of a loop.
Keyword (in Japanese) (See Japanese page) 
(in English) small delay fault / TSV / TDC / boundary scan / Design-For-Testability / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 444, DC2017-79, pp. 13-18, Feb. 2018.
Paper # DC2017-79 
Date of Issue 2018-02-13 (DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2018-02-20 - 2018-02-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Design and Test, etc. 
Paper Information
Registration To DC 
Conference Code 2018-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Reduction of Wire Length by Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC 
Sub Title (in English)  
Keyword(1) small delay fault  
Keyword(2) TSV  
Keyword(3) TDC  
Keyword(4) boundary scan  
Keyword(5) Design-For-Testability  
1st Author's Name Satoshi Hirai  
1st Author's Affiliation Tokushima University (Tokushima Univ.)
2nd Author's Name Hiroyuki Yotsuyanagi  
2nd Author's Affiliation Tokushima University (Tokushima Univ.)
3rd Author's Name Masaki Hashizume  
3rd Author's Affiliation Tokushima University (Tokushima Univ.)
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Date Time 2018-02-20 10:35:00 
Presentation Time 25 
Registration for DC 
Paper # IEICE-DC2017-79 
Volume (vol) IEICE-117 
Number (no) no.444 
Page pp.13-18 
#Pages IEICE-6 
Date of Issue IEICE-DC-2018-02-13 

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