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Paper Abstract and Keywords
Presentation 2018-01-30 11:30
[Invited Talk] Proposal and demonstration of oxide-semiconductor/(Si, SiGe, Ge) bilayer tunneling field effect transistor with type-II energy band alignment
Kimihiko Kato, Hiroaki Matsui, Hitoshi Tabata, Mitsuru Takenaka, Shinichi Takagi (Univ. of Tokyo) SDM2017-92 Link to ES Tech. Rep. Archives: SDM2017-92
Abstract (in Japanese) (See Japanese page) 
(in English) A novel bilayer tunneling field effect transistor (TFET) employing an attractive material combination of oxide-semiconductors and group-IV-semiconductors with type-II energy band alignment is proposed. The potential as a steep-slope device is systematically studied by TCAD simulation. Furthermore, the TFET operation by using n-ZnO/p-Si and n-ZnO/p-Ge tunneling junctions combined with n-ZnO junction-less channels has been experimentally demonstrated, for the first time. The careful choice of doping concentration and gate stack engineering have realized record-high ON/OFF current ratio of ~108 among TFETs reported so far and minimum S.S. of ~71 mV/dec.
Keyword (in Japanese) (See Japanese page) 
(in English) Tunneling FET / Oxide semiconductor / Group-IV semiconductor / bilayer structure / vertical tunneling / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 427, SDM2017-92, pp. 5-8, Jan. 2018.
Paper # SDM2017-92 
Date of Issue 2018-01-23 (SDM) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
技術研究報告に掲載された論文の著作権はIEICEに帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2017-92 Link to ES Tech. Rep. Archives: SDM2017-92

Conference Information
Committee SDM  
Conference Date 2018-01-30 - 2018-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SDM 
Conference Code 2018-01-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Proposal and demonstration of oxide-semiconductor/(Si, SiGe, Ge) bilayer tunneling field effect transistor with type-II energy band alignment 
Sub Title (in English)  
Keyword(1) Tunneling FET  
Keyword(2) Oxide semiconductor  
Keyword(3) Group-IV semiconductor  
Keyword(4) bilayer structure  
Keyword(5) vertical tunneling  
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Keyword(7)  
Keyword(8)  
1st Author's Name Kimihiko Kato  
1st Author's Affiliation The University of Tokyo (Univ. of Tokyo)
2nd Author's Name Hiroaki Matsui  
2nd Author's Affiliation The University of Tokyo (Univ. of Tokyo)
3rd Author's Name Hitoshi Tabata  
3rd Author's Affiliation The University of Tokyo (Univ. of Tokyo)
4th Author's Name Mitsuru Takenaka  
4th Author's Affiliation The University of Tokyo (Univ. of Tokyo)
5th Author's Name Shinichi Takagi  
5th Author's Affiliation The University of Tokyo (Univ. of Tokyo)
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Speaker
Date Time 2018-01-30 11:30:00 
Presentation Time 30 
Registration for SDM 
Paper # IEICE-SDM2017-92 
Volume (vol) IEICE-117 
Number (no) no.427 
Page pp.5-8 
#Pages IEICE-4 
Date of Issue IEICE-SDM-2018-01-23 


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