Paper Abstract and Keywords |
Presentation |
2018-01-19 10:40
Design and Implementation of 176-MHz WXGA 30-fps Real-time Optical Flow Processor Satoshi Kanda, Yu Suzuki, Masato Ito (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.) VLD2017-79 CPSY2017-123 RECONF2017-67 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper describes the design and implementation of a real-time optical flow processor using a single field-programmable gate array (FPGA) chip. By introducing the modified initial flow generation method, the successive over-relaxation (SOR) method for both layers, the optimization of the reciprocal operation method, and the image division method, it is now possible to both reduce hardware requirements and improve flow accuracy. Additionally, by introducing a pipeline structure to this processor, high-throughput hardware implementation could be achieved. Total logic cell (LC) amounts and processer memory capacity are reduced by about 8% and 16%, respectively, compared to our previous hierarchical optical flow estimation (HOE) processor. The results of our evaluation confirm that this processor can perform 30-fps wide extended graphics array (WXGA) 175.7 MHz real-time optical flow processing with a single FPGA. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Optical flow / HOE algorithm / SOR method / FPGA / Processor / / / |
Reference Info. |
IEICE Tech. Rep., vol. 117, no. 377, VLD2017-79, pp. 101-106, Jan. 2018. |
Paper # |
VLD2017-79 |
Date of Issue |
2018-01-11 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2017-79 CPSY2017-123 RECONF2017-67 |
Conference Information |
Committee |
IPSJ-ARC VLD CPSY RECONF IPSJ-SLDM |
Conference Date |
2018-01-18 - 2018-01-19 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Raiosha, Hiyoshi Campus, Keio University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
FPGA Applications, etc |
Paper Information |
Registration To |
VLD |
Conference Code |
2018-01-ARC-VLD-CPSY-RECONF-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Design and Implementation of 176-MHz WXGA 30-fps Real-time Optical Flow Processor |
Sub Title (in English) |
|
Keyword(1) |
Optical flow |
Keyword(2) |
HOE algorithm |
Keyword(3) |
SOR method |
Keyword(4) |
FPGA |
Keyword(5) |
Processor |
Keyword(6) |
|
Keyword(7) |
|
Keyword(8) |
|
1st Author's Name |
Satoshi Kanda |
1st Author's Affiliation |
Nihon University (Nihon Univ.) |
2nd Author's Name |
Yu Suzuki |
2nd Author's Affiliation |
Nihon University (Nihon Univ.) |
3rd Author's Name |
Masato Ito |
3rd Author's Affiliation |
Nihon University (Nihon Univ.) |
4th Author's Name |
Kousuke Imamura |
4th Author's Affiliation |
Kanazawa University (Kanazawa Univ.) |
5th Author's Name |
Yoshio Matsuda |
5th Author's Affiliation |
Kanazawa University (Kanazawa Univ.) |
6th Author's Name |
Tetsuya Matsumura |
6th Author's Affiliation |
Nihon University (Nihon Univ.) |
7th Author's Name |
|
7th Author's Affiliation |
() |
8th Author's Name |
|
8th Author's Affiliation |
() |
9th Author's Name |
|
9th Author's Affiliation |
() |
10th Author's Name |
|
10th Author's Affiliation |
() |
11th Author's Name |
|
11th Author's Affiliation |
() |
12th Author's Name |
|
12th Author's Affiliation |
() |
13th Author's Name |
|
13th Author's Affiliation |
() |
14th Author's Name |
|
14th Author's Affiliation |
() |
15th Author's Name |
|
15th Author's Affiliation |
() |
16th Author's Name |
|
16th Author's Affiliation |
() |
17th Author's Name |
|
17th Author's Affiliation |
() |
18th Author's Name |
|
18th Author's Affiliation |
() |
19th Author's Name |
|
19th Author's Affiliation |
() |
20th Author's Name |
|
20th Author's Affiliation |
() |
Speaker |
Author-1 |
Date Time |
2018-01-19 10:40:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2017-79, CPSY2017-123, RECONF2017-67 |
Volume (vol) |
vol.117 |
Number (no) |
no.377(VLD), no.378(CPSY), no.379(RECONF) |
Page |
pp.101-106 |
#Pages |
6 |
Date of Issue |
2018-01-11 (VLD, CPSY, RECONF) |
|