IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2018-01-19 14:30
Insertion of LC Resonator onto Cryptographic Module for Accelerated Evaluation of Side Channel Attack
Naoki Kawata, Yusuke Yano, Kengo Iokibe, Yoshitaka Toyota (Okayama Univ.) EMCJ2017-101
Abstract (in Japanese) (See Japanese page) 
(in English) Resistance evaluation for differential power analysis (DPA) and differential electromagnetic analysis (DEMA) kinds of side channel attack (SCA) methods to cryptographic ICs, costs a lot.
The reason is that at least 10 side-channel (SC) waveforms should be averaged for each plain text.
The resistance evaluation needs considerable number of plain texts, so reduction of averaging number can make a large impact on evaluation cost. This work proposed a method to reduce the averaging number by using an LC resonator.
The proposed method utilizes antiresonance of LC parallel circuit that inserted to the power distribution network of cryptographic FPGA.
It increases transfer impedance for the side-channel trace from the FPGA to the measurement port, which improves signal to noise ratio of the trace.
This SNR improvement reduces the number of averaging. The proposed method
was validated as follows. First, correlation power analysis (CPA) was performed as a representative DPA method.
Next, LC resonator was designed to resonate around the frequency band where the SC information leaked intensely.
Finally, CPA was performed again after inserting LC resonator.
Results showed that the proposed method decreased the number of averaging, providing the same level of correlation coefficients obtained before inserting LC resonator.
Before insertion of the LC resonator, correlation coefficient was 0.49 when 10 traces were averaged.
However, comparable correlation 0.53 was obtained by inserting the LC resonator with averaging of only 3 traces.
It was indicated that the proposed method could accelerate the evaluation for DPA/DEMA.
Keyword (in Japanese) (See Japanese page) 
(in English) side channel attack / evaluation cost / AES / correlation power analysis / power distribution network / LC resonance / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 384, EMCJ2017-101, pp. 77-81, Jan. 2018.
Paper # EMCJ2017-101 
Date of Issue 2018-01-11 (EMCJ) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF EMCJ2017-101

Conference Information
Committee EMCJ  
Conference Date 2018-01-18 - 2018-01-19 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Communication, PCB, Information Security, EMC 
Paper Information
Registration To EMCJ 
Conference Code 2018-01-EMCJ 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Insertion of LC Resonator onto Cryptographic Module for Accelerated Evaluation of Side Channel Attack 
Sub Title (in English)  
Keyword(1) side channel attack  
Keyword(2) evaluation cost  
Keyword(3) AES  
Keyword(4) correlation power analysis  
Keyword(5) power distribution network  
Keyword(6) LC resonance  
1st Author's Name Naoki Kawata  
1st Author's Affiliation Okayama University (Okayama Univ.)
2nd Author's Name Yusuke Yano  
2nd Author's Affiliation Okayama University (Okayama Univ.)
3rd Author's Name Kengo Iokibe  
3rd Author's Affiliation Okayama University (Okayama Univ.)
4th Author's Name Yoshitaka Toyota  
4th Author's Affiliation Okayama University (Okayama Univ.)
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Date Time 2018-01-19 14:30:00 
Presentation Time 25 
Registration for EMCJ 
Paper # IEICE-EMCJ2017-101 
Volume (vol) IEICE-117 
Number (no) no.384 
Page pp.77-81 
#Pages IEICE-5 
Date of Issue IEICE-EMCJ-2018-01-11 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan