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| Presentation | 2018-01-18 17:00 Distributed Memory Architecture for High-Level Synthesis from Erlang Kagumi Azuma, Shoki Hamana, Hidekazu Wakabayashi, Nagisa Ishiura (Kwansei Gakuin Univ.), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM)  VLD2017-75 CPSY2017-119 RECONF2017-63 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper presents a distributed memory architecture for dedicated hardware automatically synthesized from Erlang programs. Takebayashi et al. had developed a framework for generating embedded systems controllers whose behavior was specified by a subset of Erlang, where each process was mapped onto a hardware module running independently of those for the other processes. However, the resulting hardware was not of practical use because it shared a single main memory potentially accessed by all the process modules simultaneously. To address this issue, in this paper, the main memory is partitioned into banks so that each process can access its own memory independently of the other processes. In order to keep the interconnections for message passing and garbage collection to a practical size, a bus architecture is employed where requests for send and garbage collection are arbitrated by an arbiter module. From a simple Erlang specification consisting of 2 processes, a synthesizable Verilog HDL code has been generated whose behavior was confirmed by RTL simulation. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | high-level synthesis / hardware/software codesign / embedded systems / Erlang / domain-specific language / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 117, no. 377, VLD2017-75, pp. 77-82, Jan. 2018. | |
| Paper # | VLD2017-75 | |
| Date of Issue | 2018-01-11 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2017-75 CPSY2017-119 RECONF2017-63 |
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| Conference Information | |
| Committee | IPSJ-ARC VLD CPSY RECONF IPSJ-SLDM |
| Conference Date | 2018-01-18 - 2018-01-19 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Raiosha, Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2018-01-ARC-VLD-CPSY-RECONF-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Distributed Memory Architecture for High-Level Synthesis from Erlang |
| Sub Title (in English) | |
| Keyword(1) | high-level synthesis |
| Keyword(2) | hardware/software codesign |
| Keyword(3) | embedded systems |
| Keyword(4) | Erlang |
| Keyword(5) | domain-specific language |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kagumi Azuma |
| 1st Author's Affiliation | Kwansei Gakuin University (Kwansei Gakuin Univ.) |
| 2nd Author's Name | Shoki Hamana |
| 2nd Author's Affiliation | Kwansei Gakuin University (Kwansei Gakuin Univ.) |
| 3rd Author's Name | Hidekazu Wakabayashi |
| 3rd Author's Affiliation | Kwansei Gakuin University (Kwansei Gakuin Univ.) |
| 4th Author's Name | Nagisa Ishiura |
| 4th Author's Affiliation | Kwansei Gakuin University (Kwansei Gakuin Univ.) |
| 5th Author's Name | Nobuaki Yoshida |
| 5th Author's Affiliation | Advanced Science, Technology & Management Research Institute of Kyoto (ASTEM) |
| 6th Author's Name | Hiroyuki Kanbara |
| 6th Author's Affiliation | Advanced Science, Technology & Management Research Institute of Kyoto (ASTEM) |
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| Speaker | Author-1 |
| Date Time | 2018-01-18 17:00:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2017-75, CPSY2017-119, RECONF2017-63 |
| Volume (vol) | vol.117 |
| Number (no) | no.377(VLD), no.378(CPSY), no.379(RECONF) |
| Page | pp.77-82 |
| #Pages | 6 |
| Date of Issue | 2018-01-11 (VLD, CPSY, RECONF) |
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