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| Presentation | 2017-11-10 10:40 Topology maps for power dissipation minimization in LC matching circuits Naoki Sakai, Kyohei Yamada, Takashi Ohira (Toyohashi Univ. of Tech.)  MW2017-131 Link to ES Tech. Rep. Archives: MW2017-131 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Power dissipation in LC matching circuits is one problem for wireless high-power transfer system. This paper presents the topology maps which can understand the topology of the lowest power dissipation LC matching circuit inserted during source impedance 50 $¥Omega$ and load impedance $z_¥textrm{l}$. The maps draw on the smith-chart, and the topologies are 2-element L-section, 3-element $¥Pi$ type and T type, and 4-element 2-stage L-section. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | LC matching circuit / power dissipation / Poincare metric / topology map / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 117, no. 291, MW2017-131, pp. 105-110, Nov. 2017. | |
| Paper # | MW2017-131 | |
| Date of Issue | 2017-11-02 (MW) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | MW2017-131 Link to ES Tech. Rep. Archives: MW2017-131 |
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| Conference Information | |
| Committee | MW |
| Conference Date | 2017-11-09 - 2017-11-10 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Miyakojima Marin Terminal Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Microwave Technologies |
| Paper Information | |
| Registration To | MW |
| Conference Code | 2017-11-MW |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Topology maps for power dissipation minimization in LC matching circuits |
| Sub Title (in English) | |
| Keyword(1) | LC matching circuit |
| Keyword(2) | power dissipation |
| Keyword(3) | Poincare metric |
| Keyword(4) | topology map |
| Keyword(5) | |
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| Keyword(8) | |
| 1st Author's Name | Naoki Sakai |
| 1st Author's Affiliation | Toyohashi University of Technology (Toyohashi Univ. of Tech.) |
| 2nd Author's Name | Kyohei Yamada |
| 2nd Author's Affiliation | Toyohashi University of Technology (Toyohashi Univ. of Tech.) |
| 3rd Author's Name | Takashi Ohira |
| 3rd Author's Affiliation | Toyohashi University of Technology (Toyohashi Univ. of Tech.) |
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| Speaker | Author-1 |
| Date Time | 2017-11-10 10:40:00 |
| Presentation Time | 15 minutes |
| Registration for | MW |
| Paper # | MW2017-131 |
| Volume (vol) | vol.117 |
| Number (no) | no.291 |
| Page | pp.105-110 |
| #Pages | 6 |
| Date of Issue | 2017-11-02 (MW) |
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