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| Presentation | 2017-11-07 09:00 Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch Tetsuaki Fujimoto (Ritsumeikan Univ.), Wataru Takahashi, Kazutoshi Wakabayashi (NEC), Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.)  VLD2017-38 DC2017-44 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This report proposes an optimal implementation of FFT circuit for mixed grained reconfigurable architecture using via-switch. In the target architecture, the programmable routing resources are implemented in the metal layers thanks to via-switch, and as a result, rich amount of functional resources can be implemented in the substrate layer. To make full use of the rich arithmetic resources, the proposed method realizes a high-speed one-cycle-per-stage fully-parallelized processing by using $N/2$ butterfly units for $N$-point FFT. It also introduces fixed-stride-type FFT that makes the data access pattern of all stages fixed, to reduce multiplexers drastically. Compared with the Cooley-Tukey FFT, the required nets for the 64-point FFT are reduced by about 26%. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | fast Fourier transform / butterfly operation / fixed-stride-type FFT / parallelization / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 117, no. 273, VLD2017-38, pp. 67-72, Nov. 2017. | |
| Paper # | VLD2017-38 | |
| Date of Issue | 2017-10-30 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2017-38 DC2017-44 |
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| Conference Information | |
| Committee | VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM |
| Conference Date | 2017-11-06 - 2017-11-08 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kumamoto-Kenminkouryukan Parea |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2017 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2017-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch |
| Sub Title (in English) | |
| Keyword(1) | fast Fourier transform |
| Keyword(2) | butterfly operation |
| Keyword(3) | fixed-stride-type FFT |
| Keyword(4) | parallelization |
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| 1st Author's Name | Tetsuaki Fujimoto |
| 1st Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 2nd Author's Name | Wataru Takahashi |
| 2nd Author's Affiliation | NEC Corporation (NEC) |
| 3rd Author's Name | Kazutoshi Wakabayashi |
| 3rd Author's Affiliation | NEC Corporation (NEC) |
| 4th Author's Name | Takashi Imagawa |
| 4th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 5th Author's Name | Hiroyuki Ochi |
| 5th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
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| Speaker | Author-1 |
| Date Time | 2017-11-07 09:00:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2017-38, DC2017-44 |
| Volume (vol) | vol.117 |
| Number (no) | no.273(VLD), no.274(DC) |
| Page | pp.67-72 |
| #Pages | 6 |
| Date of Issue | 2017-10-30 (VLD, DC) |
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