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Paper Abstract and Keywords
Presentation 2017-11-07 09:25
On Avoiding Test Data Corruption by Optimal Scan Chain Grouping
Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara (KIT), Jun Qian (AMD) VLD2017-42 DC2017-48
Abstract (in Japanese) (See Japanese page) 
(in English) Scan shift operations cause many gates to switch simultaneously. As a result, excessive IR-drop may occur, disrupting the states of some scan flip-flops and thus corrupting test stimuli or test responses. A widely-adopted approach to solving this problem is to design multiple scan chains and shift only a group of of them at a time. This paper presents a novel scan chain grouping algorithm for reducing the probability of test data corruption caused by excessive instantaneous IR-drop on scan flip-flops. Experimental results show significant improvement of shift-power safety on all large ITC’99 benchmark circuits.
Keyword (in Japanese) (See Japanese page) 
(in English) scan test / shift power / LSI test / DFT / IR-drop / scan chain grouping / test data corruption / test power  
Reference Info. IEICE Tech. Rep., vol. 117, no. 274, DC2017-48, pp. 91-94, Nov. 2017.
Paper # DC2017-48 
Date of Issue 2017-10-30 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2017-42 DC2017-48

Conference Information
Committee VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM 
Conference Date 2017-11-06 - 2017-11-08 
Place (in Japanese) (See Japanese page) 
Place (in English) Kumamoto-Kenminkouryukan Parea 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2017 -New Field of VLSI Design- 
Paper Information
Registration To DC 
Conference Code 2017-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) On Avoiding Test Data Corruption by Optimal Scan Chain Grouping 
Sub Title (in English)  
Keyword(1) scan test  
Keyword(2) shift power  
Keyword(3) LSI test  
Keyword(4) DFT  
Keyword(5) IR-drop  
Keyword(6) scan chain grouping  
Keyword(7) test data corruption  
Keyword(8) test power  
1st Author's Name Yucong Zhang  
1st Author's Affiliation Kyushu Institute of Technology (KIT)
2nd Author's Name Stefan Holst  
2nd Author's Affiliation Kyushu Institute of Technology (KIT)
3rd Author's Name Xiaoqing Wen  
3rd Author's Affiliation Kyushu Institute of Technology (KIT)
4th Author's Name Kohei Miyase  
4th Author's Affiliation Kyushu Institute of Technology (KIT)
5th Author's Name Seiji Kajihara  
5th Author's Affiliation Kyushu Institute of Technology (KIT)
6th Author's Name Jun Qian  
6th Author's Affiliation Advanced Micro Devices, Inc. (AMD)
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Speaker
Date Time 2017-11-07 09:25:00 
Presentation Time 25 
Registration for DC 
Paper # IEICE-VLD2017-42,IEICE-DC2017-48 
Volume (vol) IEICE-117 
Number (no) no.273(VLD), no.274(DC) 
Page pp.91-94 
#Pages IEICE-4 
Date of Issue IEICE-VLD-2017-10-30,IEICE-DC-2017-10-30 


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