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Paper Abstract and Keywords
Presentation 2017-11-07 11:20
Implementation and Optimization of Parallel Prefix Adder Using Majority Function
Daiki Matsumoto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2017-46 DC2017-52
Abstract (in Japanese) (See Japanese page) 
(in English) In recent FPGAs and post CMOS devices, three-input majority operation can be efficiently realized and circuit configuration methods based on three-input majority operation are widely studied. Element reduction has been reported on adders and so on, but the precise construction method has not been shown. This manuscript shows a method of systematically realizing parallel prefix adders using majority operations and a method of reducing majority operations using the property of carry propagation. By the proposed reduction method, we achieved reduction of the number of majority operations and the power delay product as compared with the systematic realization of parallel prefix adders.
Keyword (in Japanese) (See Japanese page) 
(in English) 3 input majority function / Parallel prefix adder / Majority-Inverter-Graph / Carry propagation as a majority operation / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 273, VLD2017-46, pp. 109-114, Nov. 2017.
Paper # VLD2017-46 
Date of Issue 2017-10-30 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Download PDF VLD2017-46 DC2017-52

Conference Information
Conference Date 2017-11-06 - 2017-11-08 
Place (in Japanese) (See Japanese page) 
Place (in English) Kumamoto-Kenminkouryukan Parea 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2017 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementation and Optimization of Parallel Prefix Adder Using Majority Function 
Sub Title (in English)  
Keyword(1) 3 input majority function  
Keyword(2) Parallel prefix adder  
Keyword(3) Majority-Inverter-Graph  
Keyword(4) Carry propagation as a majority operation  
1st Author's Name Daiki Matsumoto  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Masao Yanagisawa  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Shinji Kimura  
3rd Author's Affiliation Waseda University (Waseda Univ.)
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Date Time 2017-11-07 11:20:00 
Presentation Time 25 
Registration for VLD 
Paper # IEICE-VLD2017-46,IEICE-DC2017-52 
Volume (vol) IEICE-117 
Number (no) no.273(VLD), no.274(DC) 
Page pp.109-114 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2017-10-30,IEICE-DC-2017-10-30 

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