Paper Abstract and Keywords |
Presentation |
2017-11-07 11:20
Implementation and Optimization of Parallel Prefix Adder Using Majority Function Daiki Matsumoto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2017-46 DC2017-52 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In recent FPGAs and post CMOS devices, three-input majority operation can be efficiently realized and circuit configuration methods based on three-input majority operation are widely studied. Element reduction has been reported on adders and so on, but the precise construction method has not been shown. This manuscript shows a method of systematically realizing parallel prefix adders using majority operations and a method of reducing majority operations using the property of carry propagation. By the proposed reduction method, we achieved reduction of the number of majority operations and the power delay product as compared with the systematic realization of parallel prefix adders. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
3 input majority function / Parallel prefix adder / Majority-Inverter-Graph / Carry propagation as a majority operation / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 117, no. 273, VLD2017-46, pp. 109-114, Nov. 2017. |
Paper # |
VLD2017-46 |
Date of Issue |
2017-10-30 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2017-46 DC2017-52 |
Conference Information |
Committee |
VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM |
Conference Date |
2017-11-06 - 2017-11-08 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kumamoto-Kenminkouryukan Parea |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2017 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2017-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Implementation and Optimization of Parallel Prefix Adder Using Majority Function |
Sub Title (in English) |
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Keyword(1) |
3 input majority function |
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Parallel prefix adder |
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Majority-Inverter-Graph |
Keyword(4) |
Carry propagation as a majority operation |
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1st Author's Name |
Daiki Matsumoto |
1st Author's Affiliation |
Waseda University (Waseda Univ.) |
2nd Author's Name |
Masao Yanagisawa |
2nd Author's Affiliation |
Waseda University (Waseda Univ.) |
3rd Author's Name |
Shinji Kimura |
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Waseda University (Waseda Univ.) |
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Speaker |
Author-1 |
Date Time |
2017-11-07 11:20:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2017-46, DC2017-52 |
Volume (vol) |
vol.117 |
Number (no) |
no.273(VLD), no.274(DC) |
Page |
pp.109-114 |
#Pages |
6 |
Date of Issue |
2017-10-30 (VLD, DC) |
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