Paper Abstract and Keywords |
Presentation |
2017-11-07 09:00
Flip-Flop Selection for Multi-Cycle Test with Partial Observation in Scan-Based Logic BIST Shigeyuki Oshima, Takaaki Kato (Kyutech), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyutech) VLD2017-41 DC2017-47 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A logic BIST scheme using multi-cycle test with partial observation has been proposed. In the scheme, the selection of flip-flops for partial observation plays an important role for improving the fault coverage and reducing the area overhead. This paper proposes a selection method of flip-flops for partial observation that can maximize the fault coverage under the limitation of the number of flip-flops. Experimental results show that the proposed method can obtain higher fault coverage than the existing flip-flop selection method and results in less area overhead. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
BIST / Scan Test / Multi-Cycle Test / Partial Observation / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 117, no. 274, DC2017-47, pp. 85-90, Nov. 2017. |
Paper # |
DC2017-47 |
Date of Issue |
2017-10-30 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2017-41 DC2017-47 |
Conference Information |
Committee |
VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM |
Conference Date |
2017-11-06 - 2017-11-08 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kumamoto-Kenminkouryukan Parea |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2017 -New Field of VLSI Design- |
Paper Information |
Registration To |
DC |
Conference Code |
2017-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Flip-Flop Selection for Multi-Cycle Test with Partial Observation in Scan-Based Logic BIST |
Sub Title (in English) |
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Keyword(1) |
BIST |
Keyword(2) |
Scan Test |
Keyword(3) |
Multi-Cycle Test |
Keyword(4) |
Partial Observation |
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1st Author's Name |
Shigeyuki Oshima |
1st Author's Affiliation |
Kyushu Institute of Technology (Kyutech) |
2nd Author's Name |
Takaaki Kato |
2nd Author's Affiliation |
Kyushu Institute of Technology (Kyutech) |
3rd Author's Name |
Senling Wang |
3rd Author's Affiliation |
Ehime University (Ehime Univ.) |
4th Author's Name |
Yasuo Sato |
4th Author's Affiliation |
Kyushu Institute of Technology (Kyutech) |
5th Author's Name |
Seiji Kajihara |
5th Author's Affiliation |
Kyushu Institute of Technology (Kyutech) |
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Speaker |
Author-1 |
Date Time |
2017-11-07 09:00:00 |
Presentation Time |
25 minutes |
Registration for |
DC |
Paper # |
VLD2017-41, DC2017-47 |
Volume (vol) |
vol.117 |
Number (no) |
no.273(VLD), no.274(DC) |
Page |
pp.85-90 |
#Pages |
6 |
Date of Issue |
2017-10-30 (VLD, DC) |
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