Paper Abstract and Keywords |
Presentation |
2017-11-06 10:55
Design Environment Construction for Three-Dimensional Sound Processor using High-Level Synthesis Saya Ohira, Naoki Tsuchiya, Tetsuya Matsumura (Nihon Univ.) VLD2017-28 DC2017-34 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A three-dimensional (3D) sound processor architecture that includes 3D sound processing intellectual property (IP) cores and super-directional modulation IP for consumer applications has been proposed previously. This processor can generate realistic small sound fields in arbitrary spaces by using ultrasound. The architecture is designed with high-level synthesis as the design methodology. We propose an automatic design environment for 3D sound processing IP of this processor. In this design environment, by describing the main parameters of the filter as an input file, it is possible to automatically generate high-level description of 3D sound processing IP in addition to verification by the C-based simulator. This makes it possible to automatically design RTL generation and logic synthesis afterwards and to design 3-D sound processing IP realizing required HRTF (Head Related Transfer Functions). |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Sound processer / Super-directional sound / 3-dimensional sound / High-level synthesis / FPGA / / / |
Reference Info. |
IEICE Tech. Rep., vol. 117, no. 273, VLD2017-28, pp. 7-12, Nov. 2017. |
Paper # |
VLD2017-28 |
Date of Issue |
2017-10-30 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2017-28 DC2017-34 |
Conference Information |
Committee |
VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM |
Conference Date |
2017-11-06 - 2017-11-08 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kumamoto-Kenminkouryukan Parea |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2017 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2017-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Design Environment Construction for Three-Dimensional Sound Processor using High-Level Synthesis |
Sub Title (in English) |
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Keyword(1) |
Sound processer |
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Super-directional sound |
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3-dimensional sound |
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High-level synthesis |
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FPGA |
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1st Author's Name |
Saya Ohira |
1st Author's Affiliation |
Nihon University (Nihon Univ.) |
2nd Author's Name |
Naoki Tsuchiya |
2nd Author's Affiliation |
Nihon University (Nihon Univ.) |
3rd Author's Name |
Tetsuya Matsumura |
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Nihon University (Nihon Univ.) |
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Speaker |
Author-1 |
Date Time |
2017-11-06 10:55:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2017-28, DC2017-34 |
Volume (vol) |
vol.117 |
Number (no) |
no.273(VLD), no.274(DC) |
Page |
pp.7-12 |
#Pages |
6 |
Date of Issue |
2017-10-30 (VLD, DC) |
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