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Paper Abstract and Keywords
Presentation 2017-09-26 13:55
A case study of High-level Synthesis Using Higher-order Function on Functional Language
Takuya Teraoka, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2017-35
Abstract (in Japanese) (See Japanese page) 
(in English) The growing capabilities of silicon technology and the increasing complexity of applications in recent decades have forced design methodologies and tools to raise the level of design abstraction beyond register transfer level. The most popular approach has been to develop tools that use procedual languages in a C-like language. However, coarse-grain parallelism from a C program cannot be easily extracted, hence some tools use explicitly parallel languages to design hardware. But, all these tools rely on the programmer to correctly parallelize the application and perform optimizations which often needs hardware design knowledge. In this work, we propose a high-level synthesis tool for FPGAs using DSL embedded in Haskell as the design language and search program for degree of parallelism. Haskell is a pure functional language and better fit for hardware design. We implemented higher-order functions such as map, zipWith and reduce in our DSL, which allows us to automatically extract parallelism in the design. The evaluation results show that our proposed implementation achieves 3.00 and 4.96 times speed-up in two benchmarks, array addition and summation of array, respectively, relative to a C-like language design. Moreover, we also confirme that it is consistent with the result of search program for degree of parallelism.
Keyword (in Japanese) (See Japanese page) 
(in English) High-level Synthesis / Functional Language / FPGA / / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 221, RECONF2017-35, pp. 75-80, Sept. 2017.
Paper # RECONF2017-35 
Date of Issue 2017-09-18 (RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Notes on Review This article is a technical report without peer review, and its polished version will be published elsewhere.
Download PDF RECONF2017-35

Conference Information
Committee RECONF  
Conference Date 2017-09-25 - 2017-09-26 
Place (in Japanese) (See Japanese page) 
Place (in English) DWANGO Co., Ltd. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2017-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A case study of High-level Synthesis Using Higher-order Function on Functional Language 
Sub Title (in English)  
Keyword(1) High-level Synthesis  
Keyword(2) Functional Language  
Keyword(3) FPGA  
1st Author's Name Takuya Teraoka  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Morihiro Kuga  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Motoki Amagasaki  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Masahiro Iida  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
5th Author's Name Toshinori Sueyoshi  
5th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Date Time 2017-09-26 13:55:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-RECONF2017-35 
Volume (vol) IEICE-117 
Number (no) no.221 
Page pp.75-80 
#Pages IEICE-6 
Date of Issue IEICE-RECONF-2017-09-18 

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