Paper Abstract and Keywords |
Presentation |
2017-08-01 09:45
Parallel Programming of Non-volatile Power-up States of SRAM Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya (Univ. of Tokyo), Hirofumi Shinohara (Waseda Univ.), Masaharu Kobayashi, Toshiro Hiramoto (Univ. of Tokyo) SDM2017-38 ICD2017-26 Link to ES Tech. Rep. Archives: SDM2017-38 ICD2017-26 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A technique for using an ordinary SRAM array for programmable and readable non-volatile (NV) memory is proposed. Parallel NV writing of the entire array is achieved by simply applying high-voltage stress to the power supply terminal, after storing inverted desired data in the SRAM array. On ramping up power supply voltage, the NV data will be automatically recalled into the SRAM array. Successful 2kbit NV writing is demonstrated using a device-matrix-array (DMA) TEG fabricated by 0.18μm technology. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
non-volatile memory / one-time programmable memory / CMOS / SRAM / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 117, no. 166, SDM2017-38, pp. 49-54, July 2017. |
Paper # |
SDM2017-38 |
Date of Issue |
2017-07-24 (SDM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
SDM2017-38 ICD2017-26 Link to ES Tech. Rep. Archives: SDM2017-38 ICD2017-26 |
Conference Information |
Committee |
SDM ICD ITE-IST |
Conference Date |
2017-07-31 - 2017-08-02 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hokkaido-Univ. Multimedia Education Bldg. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low voltage/low power techniques, novel devices, circuits, and applications |
Paper Information |
Registration To |
SDM |
Conference Code |
2017-07-SDM-ICD-IST |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Parallel Programming of Non-volatile Power-up States of SRAM |
Sub Title (in English) |
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Keyword(1) |
non-volatile memory |
Keyword(2) |
one-time programmable memory |
Keyword(3) |
CMOS |
Keyword(4) |
SRAM |
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1st Author's Name |
Tomoko Mizutani |
1st Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
2nd Author's Name |
Kiyoshi Takeuchi |
2nd Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
3rd Author's Name |
Takuya Saraya |
3rd Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
4th Author's Name |
Hirofumi Shinohara |
4th Author's Affiliation |
Waseda University (Waseda Univ.) |
5th Author's Name |
Masaharu Kobayashi |
5th Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
6th Author's Name |
Toshiro Hiramoto |
6th Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
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Speaker |
Author-1 |
Date Time |
2017-08-01 09:45:00 |
Presentation Time |
25 minutes |
Registration for |
SDM |
Paper # |
SDM2017-38, ICD2017-26 |
Volume (vol) |
vol.117 |
Number (no) |
no.166(SDM), no.167(ICD) |
Page |
pp.49-54 |
#Pages |
6 |
Date of Issue |
2017-07-24 (SDM, ICD) |
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