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Paper Abstract and Keywords
Presentation 2017-06-20 15:30
Evaluation of Trade-off between Performance and Area in a Variable Latency Arithmetic Circuit
Yuta Ukon, Shimpei Sato, Atsushi Takahashi (Tokyo Inst. of Tech.) CAS2017-23 VLD2017-26 SIP2017-47 MSS2017-23
Abstract (in Japanese) (See Japanese page) 
(in English) There are a lot of high load processing that is not required high accuracy at the data center. An approximate computing circuit is effective for processing at high speed and saving resources. In this research, we aim to realize an approximate computing circuit with the approach that a general-synchronous circuit which allowed variable latency continues processing even if a timing error occurs in some FFs. In the case of processing at a high-speed with a complete guarantee of a variable latency circuit, the circuit area increases due to increase replaced FFs and inserted delay elements. On the other hand, in the case of processing by allowing to occur timing errors, it may be possible to reduce replaced FFs and inserted delay elements and to process at a high speed. Therefore, according to allow error, it is necessary to determine a number of FFs to be replaced and a number of delay elements to be inserted. In this paper, we investigate a circuit area and processing performance for the delay amount inserted, and output accuracy for a number of replaced FFs by a gate level simulation for an adder. As the results, by inserting delay elements on a circuit, effective clock period is reduced by 34.92% at maximum, while a circuit area is increased by 145.83%. We also confirmed that approximate computing with decreased a maximum error and an average error can be performed by allowing only lower bit FFs to occur errors.
Keyword (in Japanese) (See Japanese page) 
(in English) General-synchronous circuit / Error detection and correction method / Variable latency / Approximate computing / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 97, VLD2017-26, pp. 119-124, June 2017.
Paper # VLD2017-26 
Date of Issue 2017-06-12 (CAS, VLD, SIP, MSS) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
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Download PDF CAS2017-23 VLD2017-26 SIP2017-47 MSS2017-23

Conference Information
Committee SIP CAS MSS VLD  
Conference Date 2017-06-19 - 2017-06-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Niigata University, Ikarashi Campus 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2017-06-SIP-CAS-MSS-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Evaluation of Trade-off between Performance and Area in a Variable Latency Arithmetic Circuit 
Sub Title (in English)  
Keyword(1) General-synchronous circuit  
Keyword(2) Error detection and correction method  
Keyword(3) Variable latency  
Keyword(4) Approximate computing  
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1st Author's Name Yuta Ukon  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
2nd Author's Name Shimpei Sato  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
3rd Author's Name Atsushi Takahashi  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
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Speaker
Date Time 2017-06-20 15:30:00 
Presentation Time 20 
Registration for VLD 
Paper # IEICE-CAS2017-23,IEICE-VLD2017-26,IEICE-SIP2017-47,IEICE-MSS2017-23 
Volume (vol) IEICE-117 
Number (no) no.96(CAS), no.97(VLD), no.98(SIP), no.99(MSS) 
Page pp.119-124 
#Pages IEICE-6 
Date of Issue IEICE-CAS-2017-06-12,IEICE-VLD-2017-06-12,IEICE-SIP-2017-06-12,IEICE-MSS-2017-06-12 


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