Paper Abstract and Keywords |
Presentation |
2017-06-20 14:50
SAT model sampling for test pattern generation considering signal transition activities Yusuke Matsunaga (Kyushu Univ.) CAS2017-21 VLD2017-24 SIP2017-45 MSS2017-21 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper presents a test pattern generation method with considering
signal transition activities using a SAT solver.
A simple SAT based test pattern generation method can only find
a single pattern per a fault, which does not consider the signal
transition activities.
The proposed method employs a randam sampling algorithm for SAT
problem, which adds randomly generated constraints to the original
problem.
The proposed method can generate arbitary number of test patterns
for one fault, so that the user can select the best one among those
patterns with respect to signal transition activities or power
consumption. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
test pattern generation / signal transition activity / SAT / random sampling / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 117, no. 97, VLD2017-24, pp. 107-112, June 2017. |
Paper # |
VLD2017-24 |
Date of Issue |
2017-06-12 (CAS, VLD, SIP, MSS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CAS2017-21 VLD2017-24 SIP2017-45 MSS2017-21 |
Conference Information |
Committee |
SIP CAS MSS VLD |
Conference Date |
2017-06-19 - 2017-06-20 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Niigata University, Ikarashi Campus |
Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
VLD |
Conference Code |
2017-06-SIP-CAS-MSS-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
SAT model sampling for test pattern generation considering signal transition activities |
Sub Title (in English) |
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Keyword(1) |
test pattern generation |
Keyword(2) |
signal transition activity |
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SAT |
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random sampling |
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1st Author's Name |
Yusuke Matsunaga |
1st Author's Affiliation |
Kyushu University (Kyushu Univ.) |
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Speaker |
Author-1 |
Date Time |
2017-06-20 14:50:00 |
Presentation Time |
20 minutes |
Registration for |
VLD |
Paper # |
CAS2017-21, VLD2017-24, SIP2017-45, MSS2017-21 |
Volume (vol) |
vol.117 |
Number (no) |
no.96(CAS), no.97(VLD), no.98(SIP), no.99(MSS) |
Page |
pp.107-112 |
#Pages |
6 |
Date of Issue |
2017-06-12 (CAS, VLD, SIP, MSS) |
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