Paper Abstract and Keywords |
Presentation |
2017-04-20 11:00
[Invited Talk]
A 4Gb LPDDR2 STT-MRAM with Compact 9F2 1T1MTJ Cell and Hierarchical Bitline Architecture Kenji Tsuchida (Toshiba), Kwangmyoung Rho, Dongkeun Kim (SK hynix), Yutaka Shirai (Toshiba), Jihyae Bae (SK hynix), Tsuneo Inaba, Hiromi Noro (Toshiba), Hyunin Moon, Sungwoong Chung (SK hynix), Kazumasa Sunouchi (Toshiba), Jinwon Park, Kiseon Park (SK hynix), Akihito Yamamoto (Toshiba), Seoungju Chung, Hyeongon Kim (SK hynix) ICD2017-3 Link to ES Tech. Rep. Archives: ICD2017-3 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The experimental 4-Gbit STT-MRAM with 9F2 1T1MTJ cell of 90nm by 90nm is presented. Hierarchical bit line architecture along with two circuit techniques contributes to total 44% reduction in bank height. In order to achieve the LPDDR2 compatible specifications even in a STT-MRAM, which has a smaller page-size than DRAM, the modifications for column command timing sequence are newly proposed. The chip size of 4Gbit STT-MRAM is 107.5 mm2, which is 14 times smaller than the previous best record. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
STT-MRAM / Perpendicular-TMR / Hierarchical Bitline Architecture / LPDDR2 Interface / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 117, no. 9, ICD2017-3, pp. 11-16, April 2017. |
Paper # |
ICD2017-3 |
Date of Issue |
2017-04-13 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ICD2017-3 Link to ES Tech. Rep. Archives: ICD2017-3 |
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