| IEICE Technical Committee Submission System Conference Paper's Information |
Online Proceedings [Sign in] Tech. Rep. Archives |
| Go Top Page | Go Previous | [Japanese] / [English] |
| Paper Abstract and Keywords | ||
| Presentation | 2017-03-01 15:55 A Design Technique for Approximate Circuits based on Artificial Neural Network Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)  VLD2016-106 |
|
| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper proposes a design technique for approximate circuits based on artificial neural network, and then evaluates the validity of our technique. In the process of circuit design, complex functions are replaced with simple neural networks so that high-performance approximate circuits can be synthesized. Our four methods to implement a neural network enable us to simplify its structure. In our experiments, which synthesize approximate circuits of an edge detection algorithm, the maximum speedup of $3times$ can be achieved with quality loss of 4%. |
|
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Approximate Computing / Approximate Circuit / Artificial Neural Network / FPGA / High-level Synthesis / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 116, no. 478, VLD2016-106, pp. 25-30, March 2017. | |
| Paper # | VLD2016-106 | |
| Date of Issue | 2017-02-22 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2016-106 |
|
| Conference Information | |
| Committee | VLD |
| Conference Date | 2017-03-01 - 2017-03-03 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2017-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Design Technique for Approximate Circuits based on Artificial Neural Network |
| Sub Title (in English) | |
| Keyword(1) | Approximate Computing |
| Keyword(2) | Approximate Circuit |
| Keyword(3) | Artificial Neural Network |
| Keyword(4) | FPGA |
| Keyword(5) | High-level Synthesis |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kazushi Kawamura |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Masao Yanagisawa |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Nozomu Togawa |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
| 4th Author's Name | |
| 4th Author's Affiliation | () |
| 5th Author's Name | |
| 5th Author's Affiliation | () |
| 6th Author's Name | |
| 6th Author's Affiliation | () |
| 7th Author's Name | |
| 7th Author's Affiliation | () |
| 8th Author's Name | |
| 8th Author's Affiliation | () |
| 9th Author's Name | |
| 9th Author's Affiliation | () |
| 10th Author's Name | |
| 10th Author's Affiliation | () |
| 11th Author's Name | |
| 11th Author's Affiliation | () |
| 12th Author's Name | |
| 12th Author's Affiliation | () |
| 13th Author's Name | |
| 13th Author's Affiliation | () |
| 14th Author's Name | |
| 14th Author's Affiliation | () |
| 15th Author's Name | |
| 15th Author's Affiliation | () |
| 16th Author's Name | |
| 16th Author's Affiliation | () |
| 17th Author's Name | |
| 17th Author's Affiliation | () |
| 18th Author's Name | |
| 18th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2017-03-01 15:55:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2016-106 |
| Volume (vol) | vol.116 |
| Number (no) | no.478 |
| Page | pp.25-30 |
| #Pages | 6 |
| Date of Issue | 2017-02-22 (VLD) |
[Return to Top Page]