Paper Abstract and Keywords |
Presentation |
2017-03-01 14:25
A Nonvolatile Flip-Flop Circuit with a Split Store/Restore Architecture for Power Gating Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2016-103 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper describes a nonvolatile Flip-Flop (NVFF) circuit to implement Nonvolatile Power Gating. We proposed a new NVFF circuit for stable store operation. We show effectiveness of area and energy dissipation by comparing the proposed circuit with conventional NVFF. Additionally, we evaluate leakage energy dissipation by using simulation for microprocessor which applied NVFF. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Power Gating / Magnetic Tunnel Junction / Nonvolatile Flip-Flop / Low Power / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 116, no. 478, VLD2016-103, pp. 7-12, March 2017. |
Paper # |
VLD2016-103 |
Date of Issue |
2017-02-22 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2016-103 |
Conference Information |
Committee |
VLD |
Conference Date |
2017-03-01 - 2017-03-03 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa Seinen Kaikan |
Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
VLD |
Conference Code |
2017-03-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Nonvolatile Flip-Flop Circuit with a Split Store/Restore Architecture for Power Gating |
Sub Title (in English) |
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Keyword(1) |
Power Gating |
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Magnetic Tunnel Junction |
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Nonvolatile Flip-Flop |
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Low Power |
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1st Author's Name |
Masaru Kudo |
1st Author's Affiliation |
Shibaura lnstitute of Technology (Shibaura Institute of Tech.) |
2nd Author's Name |
Kimiyoshi Usami |
2nd Author's Affiliation |
Shibaura lnstitute of Technology (Shibaura Institute of Tech.) |
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Speaker |
Author-1 |
Date Time |
2017-03-01 14:25:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2016-103 |
Volume (vol) |
vol.116 |
Number (no) |
no.478 |
Page |
pp.7-12 |
#Pages |
6 |
Date of Issue |
2017-02-22 (VLD) |