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Paper Abstract and Keywords
Presentation 2017-02-21 10:55
IR-Drop Analysis on Different Power Supply Network Designs
Kohei Miyase, Kiichi Hamasaki (Kyutech), Matthias Sauer (University of Freiburg), Ilia Polian (University of Passau), Bernd Becker (University of Freiburg), Xiaoqing Wen, Seiji kajihara (Kyutech) DC2016-75
Abstract (in Japanese) (See Japanese page) 
(in English) The shrinking feature size and low power design of LSI make LSI testing very difficult. Further development of LSI technology will lead to thinner wiring width, even for power supply networks and power supply voltage. Currently, vias used between the different layers of a power supply network are redundantly designed; therefore, missing only one via does not cause any problems. However, further shrinkage of feature size and low power design will lead to serious error caused by defects on the power supply network. Even though defects on power supply networks themselves do not cause an error, these defects may increase the possibility of test malfunction, a problem which has recently been actualized. In this paper, we analyze IR-drop on different power supply network designs for IWLS2005 benchmark circuits in order to understand the effect that IR-drop propagates on a chip when a via is missing. Analyzed results will be used in fault diagnosis for power related defects and power controlling test pattern generation.
Keyword (in Japanese) (See Japanese page) 
(in English) low power design / power controlling testing / power supply network design / test malfunction / fault diagnosis / test pattern generation / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 466, DC2016-75, pp. 7-10, Feb. 2017.
Paper # DC2016-75 
Date of Issue 2017-02-14 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee DC  
Conference Date 2017-02-21 - 2017-02-21 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Design and Test, etc 
Paper Information
Registration To DC 
Conference Code 2017-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) IR-Drop Analysis on Different Power Supply Network Designs 
Sub Title (in English)  
Keyword(1) low power design  
Keyword(2) power controlling testing  
Keyword(3) power supply network design  
Keyword(4) test malfunction  
Keyword(5) fault diagnosis  
Keyword(6) test pattern generation  
Keyword(7)  
Keyword(8)  
1st Author's Name Kohei Miyase  
1st Author's Affiliation Kyushu Institute of Technology (Kyutech)
2nd Author's Name Kiichi Hamasaki  
2nd Author's Affiliation Kyushu Institute of Technology (Kyutech)
3rd Author's Name Matthias Sauer  
3rd Author's Affiliation University of Freiburg (University of Freiburg)
4th Author's Name Ilia Polian  
4th Author's Affiliation University of Passau (University of Passau)
5th Author's Name Bernd Becker  
5th Author's Affiliation University of Freiburg (University of Freiburg)
6th Author's Name Xiaoqing Wen  
6th Author's Affiliation Kyushu Institute of Technology (Kyutech)
7th Author's Name Seiji kajihara  
7th Author's Affiliation Kyushu Institute of Technology (Kyutech)
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Speaker Author-1 
Date Time 2017-02-21 10:55:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2016-75 
Volume (vol) vol.116 
Number (no) no.466 
Page pp.7-10 
#Pages
Date of Issue 2017-02-14 (DC) 


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