Paper Abstract and Keywords |
Presentation |
2017-02-21 10:55
IR-Drop Analysis on Different Power Supply Network Designs Kohei Miyase, Kiichi Hamasaki (Kyutech), Matthias Sauer (University of Freiburg), Ilia Polian (University of Passau), Bernd Becker (University of Freiburg), Xiaoqing Wen, Seiji kajihara (Kyutech) DC2016-75 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The shrinking feature size and low power design of LSI make LSI testing very difficult. Further development of LSI technology will lead to thinner wiring width, even for power supply networks and power supply voltage. Currently, vias used between the different layers of a power supply network are redundantly designed; therefore, missing only one via does not cause any problems. However, further shrinkage of feature size and low power design will lead to serious error caused by defects on the power supply network. Even though defects on power supply networks themselves do not cause an error, these defects may increase the possibility of test malfunction, a problem which has recently been actualized. In this paper, we analyze IR-drop on different power supply network designs for IWLS2005 benchmark circuits in order to understand the effect that IR-drop propagates on a chip when a via is missing. Analyzed results will be used in fault diagnosis for power related defects and power controlling test pattern generation. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
low power design / power controlling testing / power supply network design / test malfunction / fault diagnosis / test pattern generation / / |
Reference Info. |
IEICE Tech. Rep., vol. 116, no. 466, DC2016-75, pp. 7-10, Feb. 2017. |
Paper # |
DC2016-75 |
Date of Issue |
2017-02-14 (DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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DC2016-75 |
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