IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2017-01-30 14:00
[Invited Talk] Novel Voltage Controlled MRAM (VCM) with Fast Read/Write Circuits for Ultra Large Level Cache
Yoichi Shiota (AIST), Hiroki Noguchi, Kazutaka Ikegami, Keiko Abe, Shinobu Fujita (Toshiba), Takayuki Nozaki, Shinji Yuasa (AIST), Yoshishige Suzuki (Osaka Univ.) SDM2016-135 Link to ES Tech. Rep. Archives: SDM2016-135
Abstract (in Japanese) (See Japanese page) 
(in English) In future processing system, the memory capacity of last level cache (LLC) must be increased, because LLC needs to cover the widening memory-bandwidth gap between multiple CPUs and the external main memory. For this purpose, non-volatile ultra-large LLCs (UL3C) having more than 100 MB should come into use. Although UL3Cs implemented with embedded DRAM have become commercially available, their usage has been constrained by their high power consumption due to their high refresh rate. Non-volatile UL3C can save this wasted energy and enables higher performance per watt in CPU/memory systems. This report presents voltage-controlled MRAM (VCM) using fast read and write circuits to achieve high-speed, low-power, and non-volatile UL3C. Our proposed circuit utilizes unipolar characteristics of voltage-torque MTJ and its voltage effects. The energy barrier is controlled by applying pulsed biases. Simulation results indicated the proposed circuits can operate even with 10% process variability at 1-sigma of MTJ fabrication and reduce operation power. Our results have shown that the proposed VCM can be used for nonvolatile UL3C.
Keyword (in Japanese) (See Japanese page) 
(in English) Voltage torque MRAM / MTJ / Low power / LLC / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 448, SDM2016-135, pp. 21-24, Jan. 2017.
Paper # SDM2016-135 
Date of Issue 2017-01-23 (SDM) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2016-135 Link to ES Tech. Rep. Archives: SDM2016-135

Conference Information
Committee SDM  
Conference Date 2017-01-30 - 2017-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SDM 
Conference Code 2017-01-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Novel Voltage Controlled MRAM (VCM) with Fast Read/Write Circuits for Ultra Large Level Cache 
Sub Title (in English)  
Keyword(1) Voltage torque MRAM  
Keyword(2) MTJ  
Keyword(3) Low power  
Keyword(4) LLC  
1st Author's Name Yoichi Shiota  
1st Author's Affiliation The National Institute of Advanced Industrial Science and Technology (AIST)
2nd Author's Name Hiroki Noguchi  
2nd Author's Affiliation Toshiba (Toshiba)
3rd Author's Name Kazutaka Ikegami  
3rd Author's Affiliation Toshiba (Toshiba)
4th Author's Name Keiko Abe  
4th Author's Affiliation Toshiba (Toshiba)
5th Author's Name Shinobu Fujita  
5th Author's Affiliation Toshiba (Toshiba)
6th Author's Name Takayuki Nozaki  
6th Author's Affiliation The National Institute of Advanced Industrial Science and Technology (AIST)
7th Author's Name Shinji Yuasa  
7th Author's Affiliation The National Institute of Advanced Industrial Science and Technology (AIST)
8th Author's Name Yoshishige Suzuki  
8th Author's Affiliation Osaka University (Osaka Univ.)
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Date Time 2017-01-30 14:00:00 
Presentation Time 30 
Registration for SDM 
Paper # IEICE-SDM2016-135 
Volume (vol) IEICE-116 
Number (no) no.448 
Page pp.21-24 
#Pages IEICE-4 
Date of Issue IEICE-SDM-2017-01-23 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan