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| Presentation | 2017-01-30 11:30 [Invited Talk] Fully Coupled 3-D Device Simulation of Negative Capacitance FinFETs for Sub 10 nm Integration Hiroyuki Ota, Tsutomu Ikegami, Junichi Hattori, Koichi Fukuda, Shinji Migita (AIST), Akira Toriumi (The Univ. of Tokyo)  SDM2016-133 Link to ES Tech. Rep. Archives: SDM2016-133 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Subthreshold operation of negative capacitance FinFETs (NC-FinFETs) at sub 10 nm gate length are analyzed with a newly developed technology computer-aided design (TCAD) simulation. This simulation fully couples the Landau-Khalatnikov (L-K) equation with the physical equations for FinFETs in 3-D. It reveals an excellent immunity against short channel effects in NC-FinFETs owing to NC-enhancement by the gate-to-drain coupling, for the first time. NC-FinFETs with a gate length of 10 nm are projected to operate with more than 26 times energy-efficiency of conventional FinFETs. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | ferroelectric / negative capacitance / technology computer-aided design / low power / subthreshold / steep / / | |
| Reference Info. | IEICE Tech. Rep., vol. 116, no. 448, SDM2016-133, pp. 13-16, Jan. 2017. | |
| Paper # | SDM2016-133 | |
| Date of Issue | 2017-01-23 (SDM) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2016-133 Link to ES Tech. Rep. Archives: SDM2016-133 |
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| Conference Information | |
| Committee | SDM |
| Conference Date | 2017-01-30 - 2017-01-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | SDM |
| Conference Code | 2017-01-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Fully Coupled 3-D Device Simulation of Negative Capacitance FinFETs for Sub 10 nm Integration |
| Sub Title (in English) | |
| Keyword(1) | ferroelectric |
| Keyword(2) | negative capacitance |
| Keyword(3) | technology computer-aided design |
| Keyword(4) | low power |
| Keyword(5) | subthreshold |
| Keyword(6) | steep |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Hiroyuki Ota |
| 1st Author's Affiliation | The National Institute of Advanced Industrial Science and Technology (AIST) |
| 2nd Author's Name | Tsutomu Ikegami |
| 2nd Author's Affiliation | The National Institute of Advanced Industrial Science and Technology (AIST) |
| 3rd Author's Name | Junichi Hattori |
| 3rd Author's Affiliation | The National Institute of Advanced Industrial Science and Technology (AIST) |
| 4th Author's Name | Koichi Fukuda |
| 4th Author's Affiliation | The National Institute of Advanced Industrial Science and Technology (AIST) |
| 5th Author's Name | Shinji Migita |
| 5th Author's Affiliation | The National Institute of Advanced Industrial Science and Technology (AIST) |
| 6th Author's Name | Akira Toriumi |
| 6th Author's Affiliation | The University of Tokyo (The Univ. of Tokyo) |
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| Speaker | Author-1 |
| Date Time | 2017-01-30 11:30:00 |
| Presentation Time | 30 minutes |
| Registration for | SDM |
| Paper # | SDM2016-133 |
| Volume (vol) | vol.116 |
| Number (no) | no.448 |
| Page | pp.13-16 |
| #Pages | 4 |
| Date of Issue | 2017-01-23 (SDM) |
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