Paper Abstract and Keywords |
Presentation |
2017-01-26 11:20
On LabVIEW FPGA Implementation of Chaotic Neuron Toshihiro Tachibana, Hideaki Okazaki (Shonan Institute of Tech.) NLP2016-101 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In recent years, FPGA (field-programmable gate array) such as dynamically reconfigurable devices has attracted attention. These semiconductor devices can be changed in action by programming. Also, it features high-speed calculation by parallel processors. The authors think to possible high-speed and high-precision processing by implementing chaotic neurons on the FPGA. For this reason, chaotic neurons were transformed into a form using a polynomial approximation or piecewise linear function so as to be suitable for FPGA implementation. In this paper, we try to calculate fast and accurate by implementing chaotic neuron. Here we use FPGA of NI myRIO device for educational institutions developed by National Instrument (NI). |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Chaotic neuron / FPGA / Piecewise polynomial / Piecewise linear function / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 116, no. 423, NLP2016-101, pp. 25-30, Jan. 2017. |
Paper # |
NLP2016-101 |
Date of Issue |
2017-01-19 (NLP) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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NLP2016-101 |
Conference Information |
Committee |
NC NLP |
Conference Date |
2017-01-26 - 2017-01-27 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kitakyushu Foundation for the Advanement of Ind. Sci. and Tech. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Implementation of Neuro Computing,Analysis and Modeling of Human Science, etc |
Paper Information |
Registration To |
NLP |
Conference Code |
2017-01-NC-NLP |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
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(See Japanese page) |
Title (in English) |
On LabVIEW FPGA Implementation of Chaotic Neuron |
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Chaotic neuron |
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FPGA |
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Piecewise polynomial |
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Piecewise linear function |
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1st Author's Name |
Toshihiro Tachibana |
1st Author's Affiliation |
Shonan Institute of Technology (Shonan Institute of Tech.) |
2nd Author's Name |
Hideaki Okazaki |
2nd Author's Affiliation |
Shonan Institute of Technology (Shonan Institute of Tech.) |
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Speaker |
Author-1 |
Date Time |
2017-01-26 11:20:00 |
Presentation Time |
25 minutes |
Registration for |
NLP |
Paper # |
NLP2016-101 |
Volume (vol) |
vol.116 |
Number (no) |
no.423 |
Page |
pp.25-30 |
#Pages |
6 |
Date of Issue |
2017-01-19 (NLP) |
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