Paper Abstract and Keywords |
Presentation |
2017-01-25 10:55
Thermal transient analysis and evaluation of three-dimensional stacked chips Shogo Yasuda, Kimiyoshi Usami (SIT) VLD2016-98 CPSY2016-134 RECONF2016-79 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
There is a three-dimensional stacking technology of LSI in technology for improving the density of LSI. Three-dimensional stack technology is capable of improving LSI integration density regardless LSI manufacturing process. However, three-dimensional stack technology of LSI has a number of problems, such as a heat problem. Since heat generated in the chip is not radiated to outside, it continues to stay in the chip. To understand this problem, in this research, we conducted transient analysis for the transfer characteristics of the heat that is generated in the three-dimensional stacked LSI. Using a three-dimensional computational fluid dynamics software “FloTHERM”, we built a model of three-dimensional stack chip and simulated with multiple conditions. From the result, we analyzed the way of transmitting the heat generated within three-dimensional stacked LSI, and how the temperature changes. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Thermal transient analysis / Three-dimensional stacked chips / / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 116, no. 415, VLD2016-98, pp. 181-186, Jan. 2017. |
Paper # |
VLD2016-98 |
Date of Issue |
2017-01-16 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2016-98 CPSY2016-134 RECONF2016-79 |
Conference Information |
Committee |
CPSY RECONF VLD IPSJ-SLDM IPSJ-ARC |
Conference Date |
2017-01-23 - 2017-01-25 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hiyoshi Campus, Keio Univ. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
FPGA Applications, etc |
Paper Information |
Registration To |
VLD |
Conference Code |
2017-01-CPSY-RECONF-VLD-SLDM-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Thermal transient analysis and evaluation of three-dimensional stacked chips |
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Thermal transient analysis |
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Three-dimensional stacked chips |
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1st Author's Name |
Shogo Yasuda |
1st Author's Affiliation |
Shibaura Institute of Technology (SIT) |
2nd Author's Name |
Kimiyoshi Usami |
2nd Author's Affiliation |
Shibaura Institute of Technology (SIT) |
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Speaker |
Author-1 |
Date Time |
2017-01-25 10:55:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2016-98, CPSY2016-134, RECONF2016-79 |
Volume (vol) |
vol.116 |
Number (no) |
no.415(VLD), no.416(CPSY), no.417(RECONF) |
Page |
pp.181-186 |
#Pages |
6 |
Date of Issue |
2017-01-16 (VLD, CPSY, RECONF) |
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